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| pd780988 subseries 8-bit single-chip microcontrollers pd780982 pd780982(a) pd780983 pd780983(a) pd780984 pd780984(a) pd780986 pd780986(a) pd780988 pd780988(a) pd78f0988a pd78f0988a(a) document no. u13029ej7v1ud00 (7th edition) date published august 2005 n cp(k) user s manual printed in japan 1997, 2000, 2002
user? manual u13029ej7v1ud 2 [memo] 3 user? manual u13029ej7v1ud 1 2 3 4 voltage application waveform at input pin w aveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 user? manual u13029ej7v1ud 4 fip and iebus are trademarks of nec electronics corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. ethernet is a trademark of xerox corporation. tron is an acronym of the realtime operating system nucleus. itron is an abbreviation of industrial tron. 5 user? manual u13029ej7v1ud the information in this document is current as of july, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ne c electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec e lectronics endeavors to enhance the quality, reliability and safety of nec e lectronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "s tandard", "special" and "specific". the "specific" quality grade applies only to nec e lectronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec e lectronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec e lectronics" as used in this statement means nec e lectronics c orporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipm ent (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "s tandard": "s pecial": "s pecific": these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. user? manual u13029ej7v1ud 6 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j02.4 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ?sucursal en espa?a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v?lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 ?succursale fran?aise ?filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 ?branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ?branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 ?united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 7 user? manual u13029ej7v1ud major revisions in this edition (1/2) page description u13029jj6v0ud00 u13029jj7v0ud00 throughout ?addition of package 64-pin plastic lqfp (14 x 14) pd780982gc- -8bs, 780983gc- -8bs, 780984gc- -8bs pd780986gc- -8bs, 780988gc- -8bs, 78f0988agc-8bs pd780982gc(a)- -8bs, 780983gc(a)- -8bs, 780984gc(a)- -8bs pd780986gc(a)- -8bs, 780988gc(a)- -8bs ?change of power supply voltage range as shown below. v dd = 4.0 to 5.5 v v dd = 3.0 to 5.5 v (expanded-specification products), v dd = 4.0 to 5.5 v (conventional products) ?change of system clock oscillation frequency (f x ) as shown below. f x = 8.38 mhz f x = 12 mhz (expanded-specification products only), f x =8.38 mhz ?change of minimum instruction execution time p.26 addition of 1.1 expanded-specification products and conventional products 1.6 pin configuration (top view) p.30 ?addition of cautions 2 and 3 to 64-pin plastic sdip (19.05 mm (750)) p.31 ?addition of cautions 2 and 3 to 64-pin plastic qfp (14 x 14), 64-pin plastic lqfp (14 x 14) p.56 3.1.2 internal data memory space addition of description on (1) internal high-speed ram and (2) internal expansion ram p.99 modification of table 5-2 relationship between cpu clock and minimum instruction execution time p.105 modification of figure 5-5 switching between system clock and cpu clock p.117 modification of figure 6-9 format of prescaler mode register 00 p.118 modification of figure 6-10 format of prescaler mode register 01 p.123 addition of figure 6-16 configuration diagram of ppg output p.123 addition of figure 6-17 ppg output operation timing p.146 modification of figure 7-7 format of timer clock select register 50 p.147 modification of figure 7-8 format of timer clock select register 51 p.147 modification of figure 7-9 format of timer clock select register 52 p.164 modification of figure 8-2 format of inverter timer control register 7 p.173 modification of table 9-1 loop detection time of watchdog timer p.174 modification of table 9-2 interval time p.175 modification of figure 9-2 format of watchdog timer clock select register p.177 modification of figure 9-4 format of oscillation stabilization time select register p.178 modification of table 9-4 loop detection time of watchdog timer p.179 modification of table 9-5 interval time of interval timer p.204 11.2 configuration of a/d converter addition of register figure to (2) a/d conversion result register 0 (adcr0) p.206 modification of figure 11-2 format of a/d converter mode register 0 p.214 11.5 notes on a/d converter addition of (6) input impedance of ani0 to ani7 pins p.232 modification of figure 12-9 format of baud rate generator control register 0 p.233 modification of figure 12-10 format of baud rate generator control register 1 user? manual u13029ej7v1ud 8 major revisions in this edition (2/2) page description 12.4.2 asynchronous serial interface (uart) mode p.234 ?modification of description p.235 ? modification of (1) register setting (c) baud rate generator control registers 0, 1 (brgc00, brgc01) p.240 modification of table 12-2 relationship between source clock of 5-bit counter and value of m (with uart00) p.240 modification of table 12-3 relationship between source clock of 5-bit counter and value of m (with uart01) p.241 modification of table 12-4 relationship between system clock and baud rate p.248 addition of remark to 12.4.3 infrared data transfer mode p.249 modification of table 12-7 baud rate that can be set in infrared data transfer mode p.254 modification of figure 13-2 format of serial operation mode register 3 p.280 addition of caution to 15.1 external device expansion function p.284 change of r/w to w in figure 15-2 format of memory expansion mode register p.294 modification of figure 16-1 format of oscillation stabilization time select register p.297 modification of figure 16-3 releasing halt mode by reset input p.300 modification of figure 16-5 releasing stop mode by reset input p.308 revision of descriptions on flash memory programming as 18.3 flash memory features p.329 18.4.5 entry ram area modification of (c) write time data p.357 addition of chapter 20 electrical specifications (expanded-specification products) p.377 addition of chapter 21 electrical specifications (conventional products) p.396 addition of chapter 22 package drawings p.399 addition of chapter 23 recommended soldering conditions p.402 modification of appendix a development tools p.414 addition of appendix b notes on designing target system u13029jj7v0ud00 u13029jj7v1ud00 p.28 modification of 1.4 ordering information p.399 modification of chapter 23 recommended soldering conditions the mark shows major revised points. 9 user? manual u13029ej7v1ud introduction target readers this manual is intended for users who wish to understand the functions of the pd780988 subseries and to design and develop application systems and programs using these microcontrollers. purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the pd780988 subseries user? manual is divided into two parts: this manual and instructions (common to the 78k/0 series). pd780988 subseries 78k/0 series user? manual user? manual (this manual) instructions pin functions cpu functions internal block functions instruction set interrupt functions explanation of instruction other on-chip peripheral functions electrical specifications how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to those who use this manual as the manual of the pd780982(a), 780983(a), 780984(a), 780986(a), 780988(a), and 78f0988a(a): unless there are functional differences, the pd780982, 780983, 780984, 780986, 780988, and 78f0988a are treated as representative devices, therefore, when this is used as a manual for the pd780982(a), 780983(a), 780984(a), 780986(a), 780988(a), and 78f0988a(a) read the product names as pd780982(a), 780983(a), 780984(a), 780986(a), 780988(a), and 78f0988a(a). to understand the functions in general: read this manual in the order of the contents. how to interpret register format: the bit name of a bit whose number is encircled is defined as a reserved word in the ra78k0, and in the header file sfrbit.in the cc78k0. when you know a register name and want to confirm its details: read appendix c register index . to know the pd789830 subseries instruction functions in detail: refer to 78k/0 series instructions user? manual (u12326e) . caution examples in this manual employ the "standard" quality grade for general electronics. when using examples in this manual for applications that require the "special" quality grade, review the quality grade of each part and/or circuit actually used. user? manual u13029ej7v1ud 10 conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780988 subseries user? manual pd780988 subseries inverter control application note 78k/0 series instructions user? manual 78k/0 series basics (i) application note this manual u13119e u12326e u12704e documents related to development software tools (user? manuals) document name ra78k0 assembler package operation language structured assembly language cc78k0 c compiler operation language sm78k0s, sm78k0 system simulator ver.2.10 or operation (windows ? based) later sm78k series system simulator ver.2.10 or later external part user open interface specifications id78k series integrated debugger ver. 2.30 or later operation (windows based) rx78k0 real-time os fundamentals installation project manager ver. 3.12 or later (windows based) caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. document no. u14445e u14446e u11789e u14297e u14298e u14611e u15006e u15185e u11537e u11536e u14610e 11 user? manual u13029ej7v1ud documents related to development hardware tools (user's manuals) document name ie-78k0-ns in-circuit emulator ie-78k0-ns-a in-circuit emulator ie-78k0-ns-pa performance board ie-78001-r-a in-circuit emulator ie-78k0-r-ex1 in-circuit emulator documents related to flash memory writing document name pg-fp3 flash memory programmer user's manual pg-fp4 flash memory programmer user's manual other related documents document name semiconductor selection guide - products and packages - semiconductor device mounting technology manual quality grades on nec semiconductor devices nec semiconductor device reliability/quality control system guide to prevent damage for semiconductor devices by electrostatic discharge (esd) note see the "semiconductor device mount manual" website (http://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. document no. u13731e u14889e to be prepared u14142e to be prepared document no. u13502e u15260e document no. x13769x c10535e c11531e c10983e c11892e user? manual u13029ej7v1ud 12 contents chapter 1 general ............................................................................................................. ............ 26 1.1 expanded-specification products and conventional products ......................................... 26 1.2 features .................................................................................................................... ............... 27 1.3 applications ................................................................................................................ ............ 27 1.4 ordering information ........................................................................................................ ...... 28 1.5 pin configuration (top view) ................................................................................................ .30 1.6 78k/0 series lineup ......................................................................................................... ....... 33 1.7 block diagram ............................................................................................................... .......... 36 1.8 functional outline .......................................................................................................... ........ 37 1.9 differences between standard quality grade products and (a) products ....................... 38 1.10 differences between flash memory products pd78f0988a and pd78f0988 .............. 38 chapter 2 pin functions ....................................................................................................... ........ 39 2.1 list of pin functions ....................................................................................................... ....... 39 2.2 description of pin functions ................................................................................................ .42 2.2.1 p00 to p03 (port 0) ....................................................................................................... .................. 42 2.2.2 p10 to p17 (port 1) ....................................................................................................... .................. 42 2.2.3 p20 to p26 (port 2) ....................................................................................................... .................. 43 2.2.4 p30 to p37 (port 3) ....................................................................................................... .................. 43 2.2.5 p40 to p47 (port 4) ....................................................................................................... .................. 43 2.2.6 p50 to p57 (port 5) ....................................................................................................... .................. 44 2.2.7 p64 to p67 (port 6) ....................................................................................................... .................. 44 2.2.8 to70 to to75 .............................................................................................................. ................... 45 2.2.9 av ref ............................................................................................................................... ............... 45 2.2.10 av dd ............................................................................................................................... ................. 45 2.2.11 av ss ............................................................................................................................... ................. 45 2.2.12 reset .................................................................................................................... ........................ 45 2.2.13 x1 and x2 ................................................................................................................ ....................... 45 2.2.14 v dd0 and v dd1 ............................................................................................................................... .. 45 2.2.15 v ss0 and v ss1 ............................................................................................................................... ... 45 2.2.16 v pp ( pd78f0988a only) ............................................................................................................... .45 2.2.17 test (mask rom version only) ............................................................................................. ........ 45 2.3 pin i/o circuits and recommended connection of unused pins ...................................... 46 chapter 3 cpu architecture .................................................................................................... .. 48 3.1 memory space ................................................................................................................ ........ 48 3.1.1 internal program memory space ............................................................................................. ........ 55 3.1.2 internal data memory space ................................................................................................ ........... 56 3.1.3 special function register (sfr) area ...................................................................................... ......... 56 3.1.4 external memory space ..................................................................................................... ............. 56 3.1.5 data memory addressing .................................................................................................... ............ 57 13 user? manual u13029ej7v1ud 3.2 processor registers ......................................................................................................... ...... 63 3.2.1 control registers ......................................................................................................... .................... 63 3.2.2 general-purpose registers ................................................................................................. ............. 66 3.2.3 special function registers (sfrs) ......................................................................................... .......... 68 3.3 instruction address addressing ........................................................................................... 73 3.3.1 relative addressing ....................................................................................................... ................. 73 3.3.2 immediate addressing ...................................................................................................... .............. 74 3.3.3 table indirect addressing ................................................................................................. ............... 75 3.3.4 register addressing ....................................................................................................... ................. 76 3.4 operand address addressing ............................................................................................... 77 3.4.1 implied addressing ........................................................................................................ .................. 77 3.4.2 register addressing ....................................................................................................... ................. 78 3.4.3 direct addressing ......................................................................................................... ................... 79 3.4.4 short direct addressing ................................................................................................... ................ 80 3.4.5 special function register (sfr) addressing ................................................................................ .... 81 3.4.6 register indirect addressing .............................................................................................. ............. 82 3.4.7 based addressing .......................................................................................................... ................. 83 3.4.8 based indexed addressing .................................................................................................. ........... 84 3.4.9 stack addressing .......................................................................................................... .................. 84 chapter 4 port functions ...................................................................................................... ..... 85 4.1 function of ports ........................................................................................................... ......... 85 4.2 configuration of ports ...................................................................................................... ...... 87 4.2.1 port 0 .................................................................................................................... .......................... 87 4.2.2 port 1 .................................................................................................................... .......................... 88 4.2.3 port 2 .................................................................................................................... .......................... 89 4.2.4 port 3 .................................................................................................................... .......................... 90 4.2.5 port 4 .................................................................................................................... .......................... 91 4.2.6 port 5 .................................................................................................................... .......................... 92 4.2.7 port 6 .................................................................................................................... .......................... 94 4.3 registers controlling port functions ................................................................................... 95 4.4 operation of port functions ................................................................................................. .97 4.4.1 writing to i/o port ....................................................................................................... ..................... 97 4.4.2 reading from i/o port ..................................................................................................... ................ 97 4.4.3 arithmetic operation of i/o port .......................................................................................... ............. 97 chapter 5 clock generator ..................................................................................................... .98 5.1 function of clock generator ................................................................................................. 98 5.2 configuration of clock generator ......................................................................................... 98 5.3 register controlling clock generator .................................................................................. 99 5.4 system clock oscillators .................................................................................................... . 100 5.4.1 system clock oscillator ................................................................................................... .............. 100 5.4.2 divider ................................................................................................................... ........................ 102 5.5 operation of clock generator ............................................................................................. 103 user? manual u13029ej7v1ud 14 5.6 changing setting of cpu clock .......................................................................................... 104 5.6.1 time required for switching cpu clock ..................................................................................... .... 104 5.6.2 switching cpu clock ....................................................................................................... .............. 105 chapter 6 16-bit timer/event counter .................................................................................. 106 6.1 outline of 16-bit timer/event counter ................................................................................ 106 6.2 function of 16-bit timer/event counter ............................................................................. 106 6.3 configuration of 16-bit timer/event counter ..................................................................... 107 6.4 registers controlling 16-bit timer/event counter ............................................................. 110 6.5 operation of 16-bit timer/event counter ........................................................................... 120 6.5.1 interval timer operation .................................................................................................. ............... 120 6.5.2 ppg output operation ...................................................................................................... ............. 122 6.5.3 pulse width measurement operation ......................................................................................... ... 124 6.5.4 external event counter operation .......................................................................................... ........ 131 6.5.5 square-wave output operation .............................................................................................. ........ 132 6.6 notes on 16-bit timer/event counter ................................................................................. 134 chapter 7 8-bit timer/event counter .................................................................................... 138 7.1 outline of 8-bit timer/event counter .................................................................................. 138 7.2 function of 8-bit timer/event counter ............................................................................... 138 7.3 configuration of 8-bit timer/event counter ....................................................................... 139 7.4 registers controlling 8-bit timer/event counter .............................................................. 142 7.5 operation of 8-bit timer/event counter ............................................................................. 149 7.5.1 interval timer (8-bit) operation .......................................................................................... ............. 149 7.5.2 external event counter operation .......................................................................................... ........ 152 7.5.3 square-wave output (8-bit resolution) operation ........................................................................... 153 7.5.4 8-bit pwm output operation ................................................................................................ .......... 154 7.5.5 interval timer (16-bit) operation ......................................................................................... ............ 157 7.6 notes on 8-bit timer/event counter ................................................................................... 159 chapter 8 10-bit inverter control timer ............................................................................ 160 8.1 outline of 10-bit inverter control timer ............................................................................. 160 8.2 function of 10-bit inverter control timer ........................................................................... 160 8.3 configuration of 10-bit inverter control timer .................................................................. 160 8.4 registers controlling 10-bit inverter control timer .......................................................... 163 8.5 operation of 10-bit inverter control timer ......................................................................... 167 chapter 9 watchdog timer ...................................................................................................... . 173 9.1 outline of watchdog timer .................................................................................................. 1 73 9.2 function of watchdog timer ............................................................................................... 173 9.3 configuration of watchdog timer ....................................................................................... 174 9.4 registers controlling watchdog timer .............................................................................. 175 9.5 operation of watchdog timer ............................................................................................. 178 15 user? manual u13029ej7v1ud 9.5.1 operation as watchdog timer ............................................................................................... ......... 178 9.5.2 operation as interval timer ............................................................................................... ............. 179 chapter 10 real-time output port ........................................................................................ 180 10.1 function of real-time output port ..................................................................................... 180 10.2 configuration of real-time output port ............................................................................. 180 10.3 registers controlling real-time output port .................................................................... 185 10.4 operation of real-time output port ................................................................................... 191 10.5 using real-time output port ............................................................................................... 2 01 10.6 notes on real-time output port ......................................................................................... 201 chapter 11 a/d converter ...................................................................................................... ... 202 1 1.1 function of a/d converter .................................................................................................. . 202 1 1.2 configuration of a/d converter ........................................................................................... 20 2 1 1.3 registers controlling a/d converter .................................................................................. 205 1 1.4 operation of a/d converter ................................................................................................. 208 1 1.4.1 basic operation of a/d converter ......................................................................................... ......... 208 1 1.4.2 input voltage and conversion result ...................................................................................... ........ 210 1 1.4.3 operation mode of a/d converter .......................................................................................... ....... 211 1 1.5 notes on a/d converter ..................................................................................................... .. 213 1 1.6 how to read a/d converter characteristics tables .......................................................... 219 chapter 12 serial interfaces uart00 and uart01 ........................................................... 222 12.1 function of serial interfaces .............................................................................................. . 222 12.2 configuration of serial interfaces ....................................................................................... 22 3 12.3 registers controlling serial interfaces .............................................................................. 227 12.4 operation of serial interfaces ............................................................................................. . 234 12.4.1 operation stop mode ...................................................................................................... .............. 234 12.4.2 asynchronous serial interface (uart) mode ............................................................................... 2 34 12.4.3 infrared data transfer mode .............................................................................................. ............ 248 chapter 13 serial interface sio3 ........................................................................................... 251 13.1 function of serial interface sio3 ........................................................................................ 25 1 13.2 configuration of serial interface ......................................................................................... 2 52 13.3 register controlling serial interface .................................................................................. 253 13.4 operation of serial interface .............................................................................................. .. 255 13.4.1 operation stop mode ...................................................................................................... .............. 255 13.4.2 3-wire serial i/o mode ................................................................................................... ................ 256 chapter 14 interrupt functions ............................................................................................ 259 14.1 types of interrupt functions ............................................................................................... 259 14.2 interrupt sources and configuration .................................................................................. 259 14.3 registers controlling interrupt functions .......................................................................... 264 user? manual u13029ej7v1ud 16 14.4 interrupt servicing operation .............................................................................................. 270 14.4.1 non-maskable interrupt request acknowledgement operation ..................................................... 270 14.4.2 maskable interrupt request acknowledgement operation ............................................................. 273 14.4.3 software interrupt request acknowledgement operation .............................................................. 275 14.4.4 multiple interrupt servicing ............................................................................................. ............... 276 14.4.5 pending interrupt requests ............................................................................................... ............. 279 chapter 15 external device expansion function ........................................................... 280 15.1 external device expansion function .................................................................................. 280 15.2 registers controlling external device expansion function ............................................ 284 15.3 timing of external device expansion function................................................................. 287 15.4 example of connection with memory ................................................................................. 292 chapter 16 standby function .................................................................................................. 2 93 16.1 standby function and configuration ................................................................................. 293 16.1.1 standby function ......................................................................................................... .................. 293 16.1.2 register controlling standby function .................................................................................... ........ 294 16.2 operation of standby function ........................................................................................... 295 16.2.1 halt mode ................................................................................................................ ................... 295 16.2.2 stop mode ................................................................................................................ .................. 298 chapter 17 reset function ..................................................................................................... .. 301 chapter 18 pd78f0988a ............................................................................................................... 305 18.1 internal memory size switching register .......................................................................... 306 18.2 internal expansion ram size switching register ............................................................. 307 18.3 flash memory characteristics ............................................................................................. 308 18.3.1 programming environment ................................................................................................ ........... 308 18.3.2 communication mode ..................................................................................................... ............. 309 18.3.3 on-board pin processing ................................................................................................ .............. 312 18.3.4 connection of adapter for flash writing ................................................................................ ........ 315 18.4 flash memory programming by self write ......................................................................... 323 18.4.1 flash memory configuration ............................................................................................... .......... 323 18.4.2 flash programming mode control register .................................................................................. .. 324 18.4.3 self-write procedure ..................................................................................................... ................. 324 18.4.4 cpu resources ............................................................................................................ ................. 328 18.4.5 entry ram area ........................................................................................................... ................. 328 18.4.6 self-write subroutines ................................................................................................... ................ 330 18.4.7 self-write circuit configuration ......................................................................................... .............. 342 chapter 19 instruction set .................................................................................................... .. 343 19.1 conventions ................................................................................................................ .......... 343 19.1.1 operand representation and description formats ......................................................................... 34 3 19.1.2 description of operation column .......................................................................................... ......... 344 17 user? manual u13029ej7v1ud 19.1.3 description of flag operation column ..................................................................................... ....... 344 19.2 operation list ............................................................................................................. .......... 345 19.3 instruction list by addressing ............................................................................................ 3 53 chapter 20 electrical specifications (expanded-specification products) ........ 357 chapter 21 electrical specifications (conventional products) .......................... 377 chapter 22 package drawings ................................................................................................ 396 chapter 23 recommended soldering conditions .......................................................... 399 appendix a development tools ............................................................................................ 402 a.1 software package ............................................................................................................ ..... 404 a.2 language processing software .......................................................................................... 404 a.3 control software ............................................................................................................ ....... 405 a.4 flash memory writing tools ................................................................................................ 40 5 a.5 debugging tools (hardware) ............................................................................................... 406 a.5.1 when using the in-circuit emulator ie-78k0-ns or ie-78k0-ns-a ............................................... 406 a.5.2 when using the in-circuit emulator ie-78001-r-a ........................................................................ 407 a.6 debugging tools (software) ................................................................................................ 40 8 a.7 embedded software ........................................................................................................... .. 409 a.8 upgrading from former in-circuit emulator for 78k/0 series to ie-78001-r-a .............. 410 a.9 package drawings for conversion socket and conversion adapter ............................... 411 appendix b notes on designing target system ................................................................ 414 appendix c register index ..................................................................................................... .... 418 c.1 register index (in alphabetical order with respect to register name) .......................... 418 c.2 register index (in alphabetical order with respect to register symbol) ...................... 421 appendix d revision history ................................................................................................... .. 424 user? manual u13029ej7v1ud 18 list of figures (1/6) figure no. title page 2-1 pin i/o circuits ............................................................................................................ ............................ 47 3-1 memory map ( pd780982) .................................................................................................................... 49 3-2 memory map ( pd780983) .................................................................................................................... 50 3-3 memory map ( pd780984) .................................................................................................................... 51 3-4 memory map ( pd780986) .................................................................................................................... 52 3-5 memory map ( pd780988) .................................................................................................................... 53 3-6 memory map ( pd78f0988a) ................................................................................................................ 54 3-7 data memory addressing ( pd780982) ................................................................................................. 57 3-8 data memory addressing ( pd780983) ................................................................................................. 58 3-9 data memory addressing ( pd780984) ................................................................................................. 59 3-10 data memory addressing ( pd780986) ................................................................................................. 60 3-11 data memory addressing ( pd780988) ................................................................................................. 61 3-12 data memory addressing ( pd78f0988a) ............................................................................................ 62 3-13 program counter configuration .............................................................................................. ................ 63 3-14 program status word configuration .......................................................................................... ............. 63 3-15 stack pointer configuration ................................................................................................ .................... 64 3-16 data saved to stack memory ................................................................................................. ................ 65 3-17 data restored from stack memory ............................................................................................ ............ 65 3-18 general-purpose register configuration ..................................................................................... ........... 67 4-1 types of ports .............................................................................................................. ........................... 85 4-2 block diagram of p00 to p03 ................................................................................................. ................. 88 4-3 block diagram of p10 to p17 ................................................................................................. ................. 88 4-4 block diagram of p20 to p26 ................................................................................................. ................. 89 4-5 block diagram of p30 to p37 ................................................................................................. ................. 90 4-6 block diagram of p40 to p47 ................................................................................................. ................. 91 4-7 block diagram of p50 ........................................................................................................ ..................... 92 4-8 block diagram of p51 to p57 ................................................................................................. ................. 93 4-9 block diagram of p64 to p67 ................................................................................................. ................. 94 4-10 format of port mode register ............................................................................................... ................. 95 4-11 format of pull-up resistor option register ................................................................................. ........... 96 5-1 clock generator block diagram ............................................................................................... .............. 98 5-2 format of processor clock control register .................................................................................. ........ 99 5-3 external circuit of system clock oscillator ................................................................................. ......... 100 5-4 examples of incorrect resonator connection .................................................................................. .... 101 5-5 switching between system clock and cpu clock ............................................................................... 1 05 6-1 block diagram of 16-bit timer/event counter 00 .............................................................................. ... 107 6-2 block diagram of 16-bit timer/event counter 01 .............................................................................. ... 108 6-3 format of 16-bit timer mode control register 00 ............................................................................. ... 111 6-4 format of 16-bit timer mode control register 01 ............................................................................. ... 112 6-5 format of capture/compare control register 00 ............................................................................... .. 113 19 user? manual u13029ej7v1ud list of figures (2/6) figure no. title page 6-6 format of capture/compare control register 01 ............................................................................... .. 114 6-7 format of timer output control register 00 .................................................................................. ....... 115 6-8 format of timer output control register 01 .................................................................................. ....... 116 6-9 format of prescaler mode register 00 ........................................................................................ ......... 117 6-10 format of prescaler mode register 01 ....................................................................................... .......... 118 6-11 format of port mode register 5 ............................................................................................. .............. 119 6-12 control register settings for interval timer operation ..................................................................... .... 120 6-13 interval timer configuration diagram ....................................................................................... ............ 121 6-14 timing of interval timer operation ......................................................................................... ............... 121 6-15 control register settings for ppg output operation ......................................................................... .. 122 6-16 configuration diagram of ppg output ........................................................................................ ......... 123 6-17 ppg output operation timing ................................................................................................ .............. 123 6-18 control register settings for pulse width measurement with free-running counter and one capture register ....................................................................................................... ............. 124 6-19 configuration diagram for pulse width measurement with free-running counter ............................. 125 6-20 timing of pulse width measurement operation with free-running counter and one capture register (with both edges specified) ....................................................................... 125 6-21 control register settings for measurement of two pulse widths with free-running counter ............ 126 6-22 cr01n capture operation with rising edge specified ........................................................................ 1 27 6-23 timing of pulse width measurement operation with free-running counter (with both edges specified) .................................................................................................... .............. 127 6-24 control register settings for pulse width measurement with free-running counter and two capture registers ...................................................................................................... ............ 128 6-25 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) .................................................................... 129 6-26 control register settings for pulse width measurement by means of restart .................................... 130 6-27 timing of pulse width measurement operation by means of restart (with rising edge specified) ................................................................................................... .............. 130 6-28 control register settings in external event counter mode .................................................................. 1 31 6-29 external event counter configuration diagram ............................................................................... ..... 132 6-30 external event counter operation timings (with rising edge specified) ............................................ 132 6-31 control register settings in square-wave output mode ..................................................................... 13 3 6-32 square-wave output operation timing ........................................................................................ ........ 133 6-33 16-bit timer counter start timing .......................................................................................... .............. 134 6-34 timing after change of compare register during timer count operation .......................................... 134 6-35 capture register data retention timing ..................................................................................... ......... 135 6-36 operation timing of ovf0n flag ............................................................................................. ............. 136 7-1 block diagram of 8-bit timer/event counter 50 ............................................................................... .... 139 7-2 block diagram of 8-bit timer/event counter 51 ............................................................................... .... 140 7-3 block diagram of 8-bit timer/event counter 52 ............................................................................... .... 140 7-4 format of 8-bit timer mode control register 50 .............................................................................. .... 143 7-5 format of 8-bit timer mode control register 51 .............................................................................. .... 144 7-6 format of 8-bit timer mode control register 52 .............................................................................. .... 145 user? manual u13029ej7v1ud 20 list of figures (3/6) figure no. title page 7-7 format of timer clock select register 50 .................................................................................... ........ 146 7-8 format of timer clock select register 51 .................................................................................... ........ 147 7-9 format of timer clock select register 52 .................................................................................... ........ 147 7-10 format of port mode register 2 ............................................................................................. .............. 148 7-11 interval timer operation timing ............................................................................................ ................ 149 7-12 external event counter operation timing (with rising edge specified) .............................................. 152 7-13 square-wave output operation timing ........................................................................................ ........ 153 7-14 pwm output operation timing ................................................................................................ ............. 155 7-15 operation timing when cr5n is changed ...................................................................................... .... 156 7-16 16-bit resolution cascade mode (with tm50 and tm51) .................................................................... 157 7-17 16-bit resolution cascade mode (with tm51 and tm52) .................................................................... 158 7-18 start timing of 8-bit timer counter ........................................................................................ .............. 159 7-19 timing after changing values of compare registers during timer count operation .......................... 159 8-1 block diagram of 10-bit inverter control timer .............................................................................. ...... 161 8-2 format of inverter timer control register 7 ................................................................................. ........ 164 8-3 format of inverter timer mode register 7 .................................................................................... ........ 165 8-4 tm7 operation timing (basic operation) ...................................................................................... ....... 169 8-5 tm7 operation timing (cmn (bfcmn) cm3 (bfcm3)) ..................................................................... 170 8-6 tm7 operation timing (cmn (bfcmn) = 000h) .................................................................................. 171 8-7 tm7 operation timing (cmn (bfcmn) = cm3 ?1/2dtm, cmn (bfcmn) > cm3 ?1/2dtm) .............. 172 9-1 watchdog timer block diagram ................................................................................................ ........... 174 9-2 format of watchdog timer clock select register .............................................................................. .. 175 9-3 format of watchdog timer mode register ...................................................................................... ..... 176 9-4 format of oscillation stabilization time select register .................................................................... .. 177 10-1 block diagram of real-time output port ..................................................................................... ......... 181 10-2 configuration of real-time output buffer register 0 ........................................................................ ... 183 10-3 configuration of real-time output buffer register 1 ........................................................................ ... 184 10-4 format of port mode register 3 ............................................................................................. .............. 185 10-5 format of real-time output port mode register 0 ............................................................................ .. 185 10-6 format of real-time output port mode register 1 ............................................................................ .. 186 10-7 format of real-time output port control register 0 ......................................................................... ... 187 10-8 format of real-time output port control register 1 ......................................................................... ... 188 10-9 format of dc control register 0 ............................................................................................ .............. 189 10-10 format of dc control register 1 ........................................................................................... ............... 190 10-11 real-time output port operation timing example (8 bits 1) ............................................................ 193 10-12 real-time output port operation timing example (6 bits 1) ............................................................ 198 1 1-1 a/d converter block diagram ................................................................................................ ............... 203 1 1-2 format of a/d converter mode register 0 .................................................................................... ....... 206 1 1-3 format of analog input channel specification register 0 .................................................................... 207 1 1-4 basic operation of a/d converter ........................................................................................... .............. 209 21 user? manual u13029ej7v1ud list of figures (4/6) figure no. title page 1 1-5 relationship between analog input voltage and a/d conversion result ............................................. 210 1 1-6 a/d conversion by hardware start (with falling edge specified) ........................................................ 211 1 1-7 a/d conversion by software start ........................................................................................... ............. 212 1 1-8 example of reducing current consumption in standby mode ............................................................ 213 1 1-9 processing analog input pin ................................................................................................ ................. 214 1 1-10 a/d conversion end interrupt request generation timing .................................................................. 21 5 11 -11 processing of av dd pin ......................................................................................................................... 21 5 1 1-12 timing of reading conversion result (when conversion result is undefined) .................................. 216 1 1-13 timing of reading conversion result (when conversion result is normal) ....................................... 216 1 1-14 example of connecting capacitor to av ref pin .................................................................................... 217 1 1-15 internal equivalent circuit of pins ani0 to ani7 .......................................................................... ......... 218 1 1-16 example of connection if signal source impedance is high ............................................................... 218 1 1-17 overall error ............................................................................................................. ............................. 220 1 1-18 quantization error ........................................................................................................ ......................... 220 1 1-19 zero-scale error .......................................................................................................... ......................... 221 1 1-20 full-scale error .......................................................................................................... ........................... 221 1 1-21 integral linearity error .................................................................................................. ........................ 221 1 1-22 differential linearity error .............................................................................................. ....................... 221 12-1 block diagram of serial interface uart00 ................................................................................... ........ 223 12-2 block diagram of uart00 baud rate generator ................................................................................ .224 12-3 block diagram of serial interface uart01 ................................................................................... ........ 225 12-4 block diagram of uart01 baud rate generator ................................................................................ .225 12-5 format of asynchronous serial interface mode register 0 .................................................................. 22 8 12-6 format of asynchronous serial interface mode register 1 .................................................................. 22 9 12-7 format of asynchronous serial interface status register 0 ................................................................. 2 30 12-8 format of asynchronous serial interface status register 1 ................................................................. 2 31 12-9 format of baud rate generator control register 0 ........................................................................... .. 232 12-10 format of baud rate generator control register 1 .......................................................................... ... 233 12-11 baud rate tolerance including sampling error (when k = 0) .............................................................. 242 12-12 asynchronous serial interface transmit/receive data format ............................................................ 243 12-13 timing of asynchronous serial interface transmission completion interrupt request generation ................................................................................................... ............ 245 12-14 timing of asynchronous serial interface reception completion interrupt request generation .......... 246 12-15 receive error timing ...................................................................................................... ...................... 247 12-16 comparison of data format in infrared data transfer mode and uart mode .................................... 248 13-1 block diagram of serial interface 3 ........................................................................................ .............. 252 13-2 format of serial operation mode register 3 ................................................................................. ....... 254 13-3 timing of 3-wire serial i/o mode ........................................................................................... ............... 258 14-1 basic configuration of interrupt function .................................................................................. ........... 262 14-2 format of interrupt request flag registers ................................................................................. ........ 265 14-3 format of interrupt mask flag register ..................................................................................... ........... 266 user? manual u13029ej7v1ud 22 14-4 format of priority specification flag register ............................................................................. ......... 267 14-5 format of external interrupt rising edge enable register and external interrupt falling edge enable register ................................................................................ ... 268 14-6 format of external interrupt rising edge enable register 5 and external interrupt falling edge enable register 5 .............................................................................. .. 269 14-7 configuration of program status word ....................................................................................... .......... 270 14-8 flowchart from non-maskable interrupt request generation to acknowledgement ............................ 271 14-9 timing of non-maskable interrupt request acknowledgement ............................................................ 271 14-10 acknowledgement operation of non-maskable interrupt request ....................................................... 272 14-11 interrupt request acknowledgement program algorithm ..................................................................... 27 4 14-12 interrupt request acknowledgement timing (minimum time) ............................................................. 275 14-13 interrupt request acknowledgement timing (maximum time) ............................................................ 275 14-14 multiple interrupt example ................................................................................................ .................... 277 14-15 pending interrupt request ................................................................................................. ................... 279 15-1 memory map when external device expansion function used .......................................................... 281 15-2 format of memory expansion mode register ................................................................................... ... 284 15-3 format of memory expansion wait setting register ........................................................................... . 285 15-4 format of memory size switching register ................................................................................... ....... 286 15-5 instruction fetch from external memory ..................................................................................... .......... 288 15-6 read timing of external memory ............................................................................................. ............ 289 15-7 write timing of external memory ............................................................................................ .............. 290 15-8 read-modify-write timing of external memory ................................................................................ .... 291 15-9 example of connecting pd780984 and memory ................................................................................ 292 16-1 format of oscillation stabilization time select register ................................................................... ... 294 16-2 releasing halt mode by interrupt request ................................................................................... ..... 296 16-3 releasing halt mode by reset input ......................................................................................... ...... 297 16-4 releasing stop mode by interrupt request ................................................................................... ..... 299 16-5 releasing stop mode by reset input ......................................................................................... ..... 300 17-1 reset function block diagram ............................................................................................... .............. 301 17-2 reset timing by reset input ................................................................................................ .............. 302 17-3 reset timing by overflow in watchdog timer ................................................................................. ..... 302 17-4 reset timing by reset input in stop mode ................................................................................... ... 302 18-1 format of memory size switching register ................................................................................... ....... 306 18-2 format of internal expansion ram size switching register ................................................................ 307 18-3 environment for writing program to flash memory ............................................................................ .. 308 18-4 communication mode selection format ........................................................................................ ....... 309 18-5 example of connection with dedicated flash programmer ................................................................. 310 18-6 v pp pin connection example ........................................................................................................ ........ 312 18-7 signal conflict (input pin of serial interface) ............................................................................ ............ 313 18-8 abnormal operation of other device ......................................................................................... ........... 313 list of figures (5/6) figure no. title page 23 user? manual u13029ej7v1ud list of figures (6/6) figure no. title page 18-9 signal conflict (reset pin) ................................................................................................ ................. 314 18-10 wiring example for flash writing adapter with 3-wire serial i/o (sio3) .............................................. 315 18-11 wiring example for flash writing adapter with 3-wire serial i/o (sio3) with handshake ................... 317 18-12 wiring example for flash writing adapter with uart (uart00) ......................................................... 319 18-13 wiring example for flash writing adapter with pseudo 3-wire serial i/o ............................................ 321 18-14 flash memory configuration ................................................................................................ ................. 323 18-15 format of flash programming mode control register ......................................................................... 324 18-16 self programming flowchart ................................................................................................ ................ 325 18-17 self-write timing ......................................................................................................... .......................... 327 18-18 self-write circuit configuration .......................................................................................... ................... 342 a-1 configuration of development tools .......................................................................................... ........... 403 a-2 ev-9200gc-64 package drawing (for reference only) ...................................................................... 411 a-3 ev-9200gc-64 footprints (for reference only) ................................................................................ .. 412 a-4 tgc-064sap package drawing (for reference only) ........................................................................ 413 b-1 distance between in-circuit emulator and conversion socket or conversion adapter (1) .................. 414 b-2 distance between in-circuit emulator and conversion socket or conversion adapter (2) .................. 415 b-3 distance between in-circuit emulator and conversion socket or conversion adapter (3) .................. 415 b-4 connection condition of target system (1) ................................................................................... ....... 416 b-5 connection condition of target system (2) ................................................................................... ....... 417 b-6 connection condition of target system (3) ................................................................................... ....... 417 user? manual u13029ej7v1ud 24 list of tables (1/2) table no. title page 1-1 differences between expanded-specification products and conventional products............................. 26 1-2 differences between standard quality grade products and (a) products ............................................. 38 1-3 differences between pd78f0988a and pd78f0988 ......................................................................... 38 2-1 types of pin i/o circuits ................................................................................................... ...................... 46 3-1 internal rom capacity ....................................................................................................... .................... 55 3-2 vector table ................................................................................................................ ............................ 55 3-3 absolute addresses of general-purpose registers ............................................................................. .. 66 3-4 special function register list .............................................................................................. .................. 69 4-1 port functions .............................................................................................................. ........................... 86 4-2 port configuration .......................................................................................................... ......................... 87 5-1 configuration of clock generator ............................................................................................ ............... 98 5-2 relationship between cpu clock and minimum instruction execution time ......................................... 99 5-3 maximum time required for switching cpu clock .............................................................................. 1 04 6-1 configuration of 16-bit timer/event counter ................................................................................. ....... 107 6-2 ti00n pin valid edge and cr00n, cr01n capture triggers ................................................................ 109 6-3 ti01n pin valid edge and cr00n capture trigger .............................................................................. . 109 7-1 configuration of 8-bit timer/event counter .................................................................................. ........ 139 8-1 configuration of 10-bit inverter control timer .............................................................................. ........ 160 9-1 loop detection time of watchdog timer ....................................................................................... ....... 173 9-2 interval time ............................................................................................................... .......................... 174 9-3 configuration of watchdog timer ............................................................................................. ............ 174 9-4 loop detection time of watchdog timer ....................................................................................... ....... 178 9-5 interval time of interval timer ............................................................................................. ................. 179 10-1 configuration of real-time output port ..................................................................................... ........... 180 10-2 operation during manipulation of real-time output buffer register 0 ................................................ 183 10-3 operation during manipulation of real-time output buffer register 1 ................................................ 184 10-4 real-time output port operation mode and output trigger ................................................................ 187 10-5 real-time output port operation mode and output trigger ................................................................ 188 10-6 relationship between settings of each bit of control register and real-time output ....................... 192 10-7 relationship between settings of each bit of control register and real-time output ....................... 197 1 1-1 configuration of a/d converter ............................................................................................. ................ 202 1 1-2 resistances and capacitances of equivalent circuit (reference values) ............................................ 218 25 user? manual u13029ej7v1ud list of tables (2/2) table no. title page 12-1 configuration of serial interfaces ......................................................................................... ................ 223 12-2 relationship between source clock of 5-bit counter and value of m (with uart00) ......................... 240 12-3 relationship between source clock of 5-bit counter and value of m (with uart01) ......................... 240 12-4 relationship between system clock and baud rate ........................................................................... 2 41 12-5 receive error causes ....................................................................................................... .................... 247 12-6 bit rate and pulse width ................................................................................................... ................... 249 12-7 baud rate that can be set in infrared data transfer mode ............................................................... 249 13-1 configuration of serial interface 3 ........................................................................................ ................ 252 14-1 interrupt source list ...................................................................................................... ....................... 260 14-2 flags corresponding to respective interrupt request sources ........................................................... 264 14-3 time from generation of maskable interrupt request to servicing ...................................................... 273 14-4 interrupt requests enabled for multiple interrupt during interrupt servicing ....................................... 276 15-1 pin functions in external memory expansion mode ............................................................................ 280 15-2 status of ports 4 and 6 in external memory expansion mode ............................................................. 280 15-3 set value of internal memory size switching register ....................................................................... .. 286 16-1 operation status in halt mode .............................................................................................. ............. 295 16-2 operation after release of halt mode ....................................................................................... ......... 297 16-3 operation status in stop mode .............................................................................................. ............ 298 16-4 operation after release of stop mode ....................................................................................... ........ 300 17-1 status of each hardware after reset ........................................................................................ ........... 303 18-1 differences between pd78f0988a and mask rom versions ........................................................... 305 18-2 set values of memory size switching register ............................................................................... ..... 306 18-3 set values of internal expansion ram size switching register .......................................................... 307 18-4 communication mode list .................................................................................................... ................ 309 18-5 pin connection list ........................................................................................................ ....................... 311 18-6 entry ram area ............................................................................................................. ....................... 328 18-7 list of self-write subroutines ............................................................................................. .................. 330 19-1 operand representation and description formats ............................................................................. .343 23-1 surface mounting type soldering conditions ................................................................................. ...... 399 23-2 insertion type soldering conditions ........................................................................................ ............. 400 a-1 upgrading from former in-circuit emulator for 78k/0 series to ie-78001-r-a .................................... 410 b-1 distance between in-circuit emulator and conversion socket or conversion adapter ....................... 414 user? manual u13029ej7v1ud 26 chapter 1 general 1.1 expanded-specification products and conventional products the expanded-specification product and conventional product refer to the following products. expanded-specification product: products with a rank note other than k ? mask rom versions for which orders were received after december 1, 2001. ? flash memory versions that were shipped after january 1, 2002. conventional product: products with rank note k ? products other than the above expanded specification products. note the rank is indicated by the 5th digit from the left in the lot number marked on the package. expanded-specification products and conventional products differ in the power supply voltage range and operating frequency ratings. the differences are shown in table 1-1. table 1-1. differences between expanded-specification products and conventional products power supply voltage (v dd ) guaranteed operating speed (operating frequency) conventional products expanded-specification products 4.5 to 5.5 v 8.38 mhz (0.238 s) 12 mhz (0.166 s) 4.0 to 5.5 v 8.38 mhz (0.238 s) 8.38 mhz (0.238 s) 3.0 to 5.5 v ? 8.38 mhz (0.238 s) remark the parenthesized values indicates the minimum instruction execution time. lot number o o o o ? year code week code nec control code rank chapter 1 general 27 user? manual u13029ej7v1ud 1.2 features internal rom and ram item program memory data memory part number internal rom flash memory internal high-speed ram internal expansion ram pd780982 16 kb 1,024 bytes pd780983 24 kb pd780984 32 kb pd780986 48 kb 1,024 bytes pd780988 60 kb pd78f0988a 60 kb note 1 1,024 bytes note 2 notes 1. 16, 24, 32, 48, or 60 kb are selectable by using the internal memory size switching register (ims). 2. 0 or 1,024 bytes are selectable by using the internal expansion ram size switching register (ixs). less emi (electro magnetic interference) noise than existing pd78014 and 78018f subseries external memory expansion space: 256 bytes (except pd780988) minimum instruction execution time: 0.166 s (@ f x = 12 mhz operation note ), 0.238 s (@ f x = 8.38 mhz operation) instruction set suitable for system control bit processing in entire address space multiply/divide instructions i/o ports: 47 a/d converter 10-bit resolution 8 channels serial interface: 3 channels uart mode: 2 channels 3-wire serial i/o mode: 1 channel timer: 7 channels 10-bit inverter control timer: 1 channel 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 3 channels watchdog timer: 1 channel vectored interrupts: 26 power supply voltage: v dd = 3.0 to 5.5 v (expanded-specification products) v dd = 4.0 to 5.5 v (conventional products) note expanded-specification products only. 1.3 applications motor control for inverter air conditioners, washing machines, refrigerators, etc. chapter 1 general user? manual u13029ej7v1ud 28 1.4 ordering information ?mask rom products part number package quality grade pd780982cw- 64-pin plastic sdip (19.05 mm (750)) standard pd780982cw- -a 64-pin plastic sdip (19.05 mm (750)) standard pd780982gc- -8bs 64-pin plastic lqfp (14 x 14) standard pd780982gc- -8bs-a 64-pin plastic lqfp (14 x 14) standard pd780983cw- 64-pin plastic sdip (19.05 mm (750)) standard pd780983cw- -a 64-pin plastic sdip (19.05 mm (750)) standard pd780983gc- -8bs 64-pin plastic lqfp (14 x 14) standard pd780983gc- -8bs-a 64-pin plastic lqfp (14 x 14) standard pd780984cw- 64-pin plastic sdip (19.05 mm (750)) standard pd780984cw- -a 64-pin plastic sdip (19.05 mm (750)) standard pd780984gc- -8bs 64-pin plastic lqfp (14 x 14) standard pd780984gc- -8bs-a 64-pin plastic lqfp (14 x 14) standard pd780986cw- 64-pin plastic sdip (19.05 mm (750)) standard pd780986cw- -a 64-pin plastic sdip (19.05 mm (750)) standard pd780986gc- -8bs 64-pin plastic lqfp (14 x 14) standard pd780986gc- -8bs-a 64-pin plastic lqfp (14 x 14) standard pd780988cw- 64-pin plastic sdip (19.05 mm (750)) standard pd780988cw- -a 64-pin plastic sdip (19.05 mm (750)) standard pd780988gc- -8bs 64-pin plastic lqfp (14 x 14) standard pd780988gc- -8bs-a 64-pin plastic lqfp (14 x 14) standard pd780982gc(a)- -8bs 64-pin plastic lqfp (14 x 14) special pd780983gc(a)- -8bs 64-pin plastic lqfp (14 x 14) special pd780984gc(a)- -8bs 64-pin plastic lqfp (14 x 14) special pd780986gc(a)- -8bs 64-pin plastic lqfp (14 x 14) special pd780988gc(a)- -8bs 64-pin plastic lqfp (14 x 14) special remarks 1. indicates rom code suffix. 2. products that have the part numbers suffixed by ?a?are lead-free products. please refer to quality grades on nec semiconductor devices (c11531e) published by nec corporation to know the specification of the quality grades of the devices and applications. chapter 1 general 29 user? manual u13029ej7v1ud ?flash memory products part number package quality grade pd78f0988acw 64-pin plastic sdip (19.05 mm (750)) standard pd78f0988acw-a 64-pin plastic sdip (19.05 mm (750)) standard pd78f0988agc-ab8 64-pin plastic qfp (14 x 14) standard pd78f0988agc-ab8-a 64-pin plastic qfp (14 x 14) standard pd78f0988agc-8bs 64-pin plastic lqfp (14 x 14) standard pd78f0988agc-8bs-s 64-pin plastic lqfp (14 x 14) standard pd78f0988agc(a)-ab8 64-pin plastic qfp (14 x 14) special remark products that have the part numbers suffixed by ?a?are lead-free products. please refer to quality grades on nec semiconductor devices (c11531e) published by nec corporation to know the specification of the quality grades of the devices and applications. chapter 1 general user? manual u13029ej7v1ud 30 1.5 pin configuration (top view) 64-pin plastic sdip (19.05 mm (750)) cautions 1. connect the test pin directly to v ss0 . 2. connect the v pp pin directly to the v ss0 pin in normal operation mode. 3. connect the v pp pin to v ss0 via a 10 k ? pull-down resistor in the flash memory writing mode. 4. the 64-pin plastic sdip (19.5 mm (750)) package is not supported for special quality grade products. remarks 1. the pin connection in parentheses is for the pd78f0988a. 2. when the pd780988 subseries is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50 p51/sck p52/si p53/so p54/ti000/to00/intp4 p55/ti010/intp5 p56/ti001/to01/intp6 p57/ti011/intp7 v ss0 v dd0 to70 to71 to72 to73 to74 to75 p20/rxd00 p21/txd00 p22/rxd01 p23/txd01 p24/ti50/to50 p25/ti51/to51 p26/ti52/to52 v dd1 p67/astb p66/wait p65/wr p64/rd p37/rtp7 p36/rtp6 p35/rtp5 p34/rtp4 p33/rtp3 p32/rtp2 p31/rtp1 p30/rtp0 p01/intp1 p00/intp0/toff7 v ss1 x1 x2 test (v pp ) p03/intp3/adtrg p02/intp2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 chapter 1 general 31 user? manual u13029ej7v1ud 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p50 p51/sck p52/si p53/so p54/ti000/to00/intp4 p55/ti010/intp5 p56/ti001/to01/intp6 p57/ti011/intp7 v ss0 v dd0 to70 to71 to72 to73 to74 to75 p33/rtp3 p32/rtp2 p31/rtp1 p30/rtp0 p01/intp1 p00/intp0/toff7 v ss1 x1 x2 test (v pp ) p03/intp3/adtrg p02/intp2 reset av dd av ref p10/ani0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p20/rxd00 p21/txd00 p22/rxd01 p23/txd01 p24/ti50/to50 p25/ti51/to51 p26/ti52/to52 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p37/rtp7 p36/rtp6 p35/rtp5 p34/rtp4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-pin plastic qfp (14 x 14) 64-pin plastic lqfp (14 x 14) cautions 1. connect the test pin directly to v ss0 . 2. connect the v pp pin directly to the v ss0 pin in normal operation mode. 3. connect the v pp pin to v ss0 via a 10 k ? pull-down resistor in the flash memory writing mode. chapter 1 general user? manual u13029ej7v1ud 32 ad0 to ad7: address/data bus adtrg: ad trigger input ani0 to ani7: analog input astb: address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground intp0 to intp7: external interrupt input p00 to p03: port 0 p10 to p17: port 1 p20 to p26: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p64 to p67: port 6 rd: read strobe reset: reset rtp0 to rtp7: real-time port rxd00, rxd01: receive data sck: serial clock si: serial input so: serial output test: test ti000, ti001, ti010, ti011, ti50 to ti52: timer input to00, to01, to50 to to52, to70 to to75: timer output toff7: timer output off txd00, txd01: transmit data v dd0 , v dd1 : power supply v pp : programming power supply v ss0 , v ss1 :g round wait: wait wr: write strobe x1, x2: crystal remarks 1. the pin connection in parentheses is for the pd78f0988a. 2. when the pd780988 subseries is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. chapter 1 general 33 user? manual u13029ej7v1ud remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. 1.6 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. pd78054 with iebus tm controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited function pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter control circuit and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip can controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 pd780308 with enhanced display function and timer. segment signal output: 40 pins max. on-chip can controller specialized for can controller function 80-pin pd780703y pd780702y 64-pin pd780816 pd780344 with enhanced a/d converter 100-pin 100-pin pd780344 pd780344y pd780354 pd780354y chapter 1 general user? manual u13029ej7v1ud 34 the major functional differences among the subseries are listed below. ? non-y subseries function rom timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k ? ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd78014h 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter pd780988 16 k to 60 k 3 ch note ? ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v control vfd pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780354 24 k to 32 k 4 ch 1 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 66 1.8 v drive pd780344 8 ch pd780338 48 k to 60 k 3 ch 2 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k bus pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v interface pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v supported pd780816 32 k to 60 k 2 ch 12 ch 2 ch (uart: 1 ch) 46 4.0 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control dash- pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v board control pd780828b 32 k to 60 k 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value capacity (bytes) chapter 1 general 35 user? manual u13029ej7v1ud ? y subseries function timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78078y 48 k to 60 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch, i 2 c: 1 ch) 88 1.8 v pd78070ay 61 2.7 v pd780018ay 48 k to 60 k ? ch (i 2 c: 1 ch) 88 pd780058y 24 k to 60 k 2 ch 2 ch 3 ch (time-division uart: 1 ch, i 2 c: 1 ch ) 68 1.8 v pd78058fy 48 k to 60 k 3 ch (uart: 1 ch, i 2 c: 1 ch) 69 2.7 v pd78054y 16 k to 60 k 2.0 v pd780078y 48 k to 60 k 2 ch 8 ch 4 ch (uart: 2 ch, i 2 c: 1 ch) 52 1.8 v pd780034ay 8 k to 32 k 1 ch 3 ch (uart: 1 ch, i 2 c: 1 ch) 51 pd780024ay 8 ch pd78018fy 8 k to 60 k 2 ch (i 2 c: 1 ch) 53 lcd pd780354y 24 k to 32 k 4 ch 1 ch 1 ch 1 ch 8 ch 4 ch (uart: 1 ch, 66 1.8 v drive pd780344y 8 ch i 2 c: 1 ch) pd780308y 48 k to 60 k 2 ch 3 ch (time-division uart: 1 ch, i 2 c: 1 ch) 57 2.0 v pd78064y 16 k to 32 k 2 ch (uart: 1 ch, i 2 c: 1 ch) bus pd780701y 60 k 3 ch 2 ch 1 ch 1 ch 16 ch 4 ch (uart: 1 ch, i 2 c: 1 ch) 67 3.5 v interface pd780703y supported pd780833y 65 4.5 v remark functions other than the serial interface are common to both the y and non-y subseries. v dd min. value rom capacity (bytes) chapter 1 general user? manual u13029ej7v1ud 36 watchdog timer a/d converter ani0/p10 to ani7/p17 av dd av ss av ref adtrg/intp3/p03 78k/0 cpu core rom flash ( memory ) ram v dd0 , v dd1 v ss0 , v ss1 test port 0 p00 to p03 port 2 p20 to p26 port 3 p30 to p37 port 4 p40 to p47 port 5 p50 to p57 port 6 p64 to p67 external access ad0/p40 to ad7/p47 rd/p64 wr/p65 wait/p66 astb/p67 system control reset x1 x2 16-bit timer/ event counter 01 ti001/to01/intp6/p56 ti011/intp7/p57 16-bit timer/ event counter 00 ti000/to00/intp4/p54 ti010/intp5/p55 8-bit timer/ event counter 51 to51/ti51/p25 8-bit timer/ event counter 52 to52/ti52/p26 real-time output port rtp0/p30 to rtp7/p37 uart00 txd00/p21 rxd00/p20 rxd01/p22 uart01 txd01/p23 sio3 si/p52 sck/p51 so/p53 interrupt control intp1/p01, intp2/p02 intp0/toff7/p00 intp3/adtrg/p03 intp4/ti000/to00/p54 intp5/ti010/p55 intp7/ti011/p57 intp6/ti001/to01/p56 real-time pulse unit to70 to to75 port 1 p10 to p17 (v pp ) 8-bit timer/ event counter 50 to50/ti50/p24 1.7 block diagram remarks 1. the internal rom and ram capacities differ depending on the product. 2. the pin connection in parentheses is for the pd78f0988a. chapter 1 general 37 user? manual u13029ej7v1ud 1.8 functional outline pd780982 pd780983 pd780984 pd780986 pd780988 pd78f0988a rom mask rom flash memory 16 kb 24 kb 32 kb 48 kb 60 kb 60 kb note 1 high-speed ram 1024 bytes expansion ram none 1024 bytes 1024 bytes note 2 memory space 64 kb general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction on-chip minimum instruction execution time variable function execution time ?expanded-specification products 0.166 s/0.33 s/0.66 s/1.3 s/2.6 s (@ 12 mhz operation with system clock, v dd = 4.5 to 5.5 v) 0.238 s/0.48 s/0.96 s/1.9 s/3.8 s (@ 8.38 mhz operation with system clock) ?conventional products 0.238 s/0.48 s/0.96 s/1.9 s/3.8 s (@ 8.38 mhz operation with system clock) instruction set ?16-bit operation ?multiply/divide (8 bits 8 bits, 16 bits 8 bits) ?bit manipulation (set, reset, test, boolean operation) ?bcd adjust, etc. i/o ports total: 47 ?cmos inputs: 8 ?cmos i/o: 39 real-time output ports ?8 bits 1 or 4 bits 2 ?6 bits 1 or 4 bits 1 a/d converter ?10-bit resolution 8 channels serial interface ?uart mode: 2 channels ?3-wire serial i/o mode: 1 channel timer ?16-bit timer/event counter: 2 channels ?8-bit timer/event counter: 3 channels ?10-bit inverter control timer: 1 channel ?watchdog timer: 1 channel timer outputs 11 (general-purpose outputs: 5, inverter control outputs: 6) maskable internal: 16, external: 8 non-maskable internal: 1 software 1 power supply voltage ?v dd = 3.0 to 5.5 v (expanded-specification products) ?v dd = 4.0 to 5.5 v (conventional products) operating ambient temperature t a = ?0 to +85 c package ?64-pin plastic sdip (19.05 mm (750)) note 3 ?64-pin plastic qfp (14 x 14) ?64-pin plastic lqfp (14 x 14) notes 1. the capacity of the flash memory can be changed using the internal memory size select register (ims). 2. the capacity of the internal expansion ram can be changed using the internal expansion ram size select register (ixs). 3. standard quality grade products only. item part number internal memory vectored interrupt sources chapter 1 general user? manual u13029ej7v1ud 38 the table below shows the outline of timer/event counters (for details, refer to chapter 6 16-bit timer/event counter, chapter 7 8-bit timer/event counter, chapter 8 10-bit inverter control timer, chapter 9 watchdog timer ) . 16-bit timer/ 8-bit timer/ 10-bit inverter watchdog timer event counter event counter control timer operation interval timer 2 channels 3 channels 1 channel 1 channel note mode external event counter ? function timer output ? pwm output ppg output pulse width measurement square-wave output ? interrupt request ? ? note the watchdog timer can perform either the watchdog timer function or the interval timer function. 1.9 differences between standard quality grade products and (a) products the differences between standard grade products ( pd780982, 780983, 780984, 780986, 780988, 78f0988a) and (a) products ( pd780982(a), 780983(a), 780984(a), 780986(a), 780988(a), 78f0988a(a)) are shown in table 1-2. table 1-2. differences between standard quality grade products and (a) products part number standard products (a) products item quality grade standard special package ?64-pin plastic sdip (19.05 mm (750)) ?64-pin plastic qfp (14 x 14) ?64-pin plastic qfp (14 x 14) ?64-pin plastic lqfp (14 x 14) ?64-pin plastic lqfp (14 x 14) 1.10 differences between flash memory products pd78f0988a and pd78f0988 table 1-3 shows the differences between the pd78f0988a and pd78f0988 (old product). table 1-3. differences between pd78f0988a and pd78f0988 part number pd78f0988a pd78f0988 (old product) item flash memory area 2 areas 3 areas 0: 0 to 1fffh 0: 0 to 1fffh 1: 2000h to efffh 1: 2000h to 7fffh 2: 8000h to efffh quality grade ?standard standard ?special 64-pin plastic qfp (14 x 14) 39 user? manual u13029ej7v1ud chapter 2 pin functions 2.1 list of pin functions (1) port pins p00 i/o port 0 input intp0/toff7 p01 4-bit i/o port intp1 p02 input/output can be specified in 1-bit units. intp2 p03 use of an on-chip pull-up resistor can be specified by a software setting. intp3/adtrg p10 to p17 input port 1 input ani0 to ani7 8-bit input only port p20 i/o port 2 input rxd00 p21 7-bit i/o port txd00 p22 input/output can be specified in 1-bit units. rxd01 p23 use of an on-chip pull-up resistor can be specified by a software setting. txd01 p24 ti50/to50 p25 ti51/to51 p26 ti52/to52 p30 to p37 i/o port 3 input rtp0 to rtp7 8-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. p50 i/o port 5 input p51 8-bit i/o port sck p52 input/output can be specified in 1-bit units. si p53 leds can be driven directly. so p54 use of an on-chip pull-up resistor can be specified by a software setting. intp4/ti000/to00 p55 intp5/ti010 p56 intp6/ti001/to01 p57 intp7/ti011 p64 i/o port 6 input rd p65 4-bit i/o port wr p66 input/output can be specified in 1-bit units. wait p67 use of an on-chip pull-up resistor can be specified by a software setting. astb pin name i/o function after reset alternate function chapter 2 pin functions user? manual u13029ej7v1ud 40 (2) non-port pins (1/2) intp0 input external interrupt request input for which the valid edge (rising input p00/toff7 intp1 edge, falling edge, or both rising and falling edges) can be input p01 intp2 specified input p02 intp3 input p03/adtrg intp4 input p54/ti000/to00 intp5 input p55/ti010 intp6 input p56/ti001/to01 intp7 input p57/ti011 ti50 input external count clock input to 8-bit timer/event counter 50 input p24/to50 ti51 external count clock input to 8-bit timer/event counter 51 input p25/to51 ti52 external count clock input to 8-bit timer/event counter 52 input p26/to52 ti000 external count clock input to 16-bit timer/event counter 00 input p54/intp4/to00 capture trigger input to capture register (cr000, cr010) in 16-bit timer/event counter 00 ti010 capture trigger input to capture register (cr000) in 16-bit timer input p55/intp5 /event counter 00 ti001 external count clock input to 16-bit timer/event counter 01 input p56/intp6/to01 capture trigger input to capture register (cr001, cr011) in 16-bit timer/event counter 01 ti011 capture trigger input to capture register (cr001) in 16-bit timer input p57/intp7 /event counter 01 to50 output 8-bit timer/event counter 50 output input p24/ti50 to51 8-bit timer/event counter 51 output input p25/ti51 to52 8-bit timer/event counter 52 output input p26/ti52 to00 16-bit timer/event counter 00 output input p54/intp4 /ti000 to01 16-bit timer/event counter 01 output input p56/intp6 /ti001 rtp0 to rtp7 output real-time output port that outputs pulses in synchronization with input p30 to p37 trigger signals output from the real-time pulse unit txd00 output asynchronous serial interface serial data output input p21 txd01 input p23 rxd00 input asynchronous serial interface serial data input input p20 rxd01 input p22 sck i/o serial interface serial clock input/output input p51 si input serial interface serial data input input p52 so output serial interface serial data output input p53 ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input external trigger signal input to the a/d converter input p03/intp3 to70 to to75 output timer output for the 3-phase pwm inverter control hi-z toff7 input external input to stop timer output (to70 to to75) input p00/intp0 ad0 to ad7 i/o address/data bus for when memory is expanded externally input p40 to p47 rd output strobe signal output for external memory read operation input p64 wr strobe signal output for external memory write operation input p65 wait input wait insertion when accessing external memory input p66 astb output strobe output that externally latches address information output input p67 to ports 4 and 5 to access external memory pin name i/o function after reset alternate function chapter 2 pin functions 41 user? manual u13029ej7v1ud av ref input a/d converter reference voltage input av dd a/d converter analog power supply av ss a/d converter ground potential reset input system reset input x1 input connection of crystal for system clock oscillation x2 v dd0 positive power supply for ports v ss0 ground potential for ports v dd1 positive power supply (except for ports) v ss1 ground potential (except for ports) test test mode set pin. connect to v ss0 directly v pp note high-voltage application for program write/verify. directly connect this pin to v ss0 in normal operation mode. note pd78f0988a only pin name i/o function after reset alternate function (2) non-port pins (2/2) chapter 2 pin functions user? manual u13029ej7v1ud 42 2.2 description of pin functions 2.2.1 p00 to p03 (port 0) these pins constitute a 4-bit i/o port, port 0. in addition, these pins are also used to input external interrupt request signals, a timer output stop external signal and an external trigger signal of the a/d converter. port 0 can be set in the following operation modes in 1-bit units. (1) port mode in this mode, p00 to p03 function as a 4-bit i/o port which can be set to input or output in 1-bit units by using port mode register 0 (pm0). an internal pull-up resistor can be used if so specified by pull-up resistor option register 0 (pu0). (2) control mode in this mode, p00 to p03 are used to input external interrupt requests, a timer output stop external signal, and an external trigger signal of the a/d converter. (a) intp0 to intp3 these pins are external interrupt request input pins for which the valid edge can be specified (rising edge, falling edge, and both rising and falling edges). intp2 also functions as an external trigger signal input pin of the real-time output port when a valid edge is input. (b) toff7 external input pin to stop timer output (to70 to to75). (c) adtrg external trigger signal input pin of the a/d converter. 2.2.2 p10 to p17 (port 1) these pins constitute an 8-bit input port, port 1. in addition to the general-purpose input port function, these pins also serve as the analog input pins of the a/d converter. (1) port mode in this mode, p10 to p17 function as an 8-bit input port. (2) control mode in this mode, p10 to p17 function as the analog input pins (ani0 to ani7) of the a/d converter. chapter 2 pin functions 43 user? manual u13029ej7v1ud 2.2.3 p20 to p26 (port 2) these pins constitute a 7-bit i/o port, port 2. in addition, these pins are also used as the serial interface i/o pins, and the timer i/o pins. port 2 can be set in the following operation modes in 1-bit units. (1) port mode in this mode, p20 to p26 function as a 7-bit i/o port which can be set to input or output in 1-bit units by using port mode register 2 (pm2). an internal pull-up resistor can be used if so specified by pull-up resistor option register 2 (pu2). (2) control mode in this mode, p20 to p26 function as the serial interface i/o pins, and timer i/o pins. (a) rxd00, rxd01, txd00, txd01 serial data i/o pins of the serial interface. (b) ti50 to ti52 external count clock input pins of 8-bit timer/event counters 50 to 52. (c) to50 to to52 output pins of 8-bit timer/event counters 50 to 52. 2.2.4 p30 to p37 (port 3) these pins constitute an 8-bit i/o port, port 3. in addition, they also function as a real-time output port. port 3 can be set in the following operation modes in 1-bit units. (1) port mode in this mode, p30 to p37 function as an 8-bit i/o port which can be set to input or output in 1-bit units by using port mode register 3 (pm3). an internal pull-up resistor can be used if so specified by pull-up resistor option register 3 (pu3). (2) control mode in this mode, p30 to p37 are used as a real-time output port (rtp0 to rtp7) that outputs data in synchronization with a trigger. 2.2.5 p40 to p47 (port 4) these pins constitute an 8-bit i/o port, port 4. in addition, they also function as an address/data bus. port 4 can be set in the following operation modes in 1-bit units. (1) port mode in this mode, p40 to p47 function as an 8-bit i/o port which can be set to input or output in 1-bit units by using port mode register 4 (pm4). an internal pull-up resistor can be used if so specified by pull-up resistor option register 4 (pu4). (2) control mode in this mode, p40 to p47 function as the address/data bus pins (ad0 to ad7) in the external memory expansion mode. chapter 2 pin functions user? manual u13029ej7v1ud 44 2.2.6 p50 to p57 (port 5) these pins constitute an 8-bit i/o port, port 5. in addition, these pins also function as the serial interface clock and i/o, data i/o, timer i/o, and external interrupt request input pins. these pins can directly drive leds. port 5 can be set in the following operation modes in 1-bit units. (1) port mode in this mode, p50 to p57 function as an 8-bit i/o port which can be set to input or output in 1-bit units by using port mode register 5 (pm5). an internal pull-up resistor can be used if so specified by pull-up resistor option register 5 (pu5). (2) control mode in this mode, p50 to p57 function as the serial interface clock and data i/o, timer i/o and external interrupt request input pins. (a) sck serial interface? serial clock i/o pins. (b) si, so serial interface? serial data i/o pins. (c) ti000, ti001 the pin that inputs the external counter clock to 16-bit timer/event counters 00 and 01 and the pin that inputs the capture trigger signal to the capture register of 16-bit timer/event counters 00 and 01. (d) ti010 and ti011 the pins that input the capture trigger signal to the capture register of 16-bit timer/event counters 00 and 01. (e) to00 and to01 output pins of 16-bit timer/event counters 00 and 01. (f) intp4 to intp7 external interrupt request input pins for which valid edges (rising edge, falling edge, and both rising and falling edges) can be specified. 2.2.7 p64 to p67 (port 6) these pins constitute a 4-bit i/o port, port 6, which can also be used to output control signals in the external memory expansion mode. port 6 can be set in the following operation modes in 1-bit units. (1) port mode in this mode, p64 to p67 function as a 4-bit i/o port which can be set to input or output in 1-bit units by using port mode register 6 (pm6). an internal pull-up resistor can be used if so specified by pull-up resistor option register 6 (pu6). chapter 2 pin functions 45 user? manual u13029ej7v1ud (2) control mode in this mode, p64 to p67 function as control signal output pins (rd, wr, wait, and astb) in the external memory expansion mode. the pins used as control signal output pins are automatically disconnected from internal pull-up resistors. caution if the external wait state is not used in the external memory expansion mode, p66 can be used as an i/o port pin. 2.2.8 to70 to to75 these are the timer output pins for 3-phase pwm inverter control. 2.2.9 av ref this pin inputs a reference voltage to the a/d converter. connect this pin to v ss0 when the a/d converter is not used. 2.2.10 av dd this is the analog power supply pin of the a/d converter. keep this pin at the same voltage as the v dd0 pin even when the a/d converter is not used. 2.2.11 av ss this is the ground pin of the a/d converter. keep this pin at the same voltage as the v ss0 pin even when the a/d converter is not used. 2.2.12 reset this pin inputs an active-low system reset signal. 2.2.13 x1 and x2 these pins are used to connect a crystal resonator for system clock oscillation. to supply an external clock, input the clock to x1 and input the inverted signal to x2. 2.2.14 v dd0 and v dd1 v dd0 is the positive power supply pin for ports. v dd1 is the positive power supply pin for blocks other than ports. 2.2.15 v ss0 and v ss1 v ss0 is the ground pin for ports. v ss1 is the ground pin for blocks other than ports. 2.2.16 v pp ( pd78f0988a only) a high voltage should be applied to this pin when the program is written or verified. directly connect this pin to v ss0 in the normal operation mode. 2.2.17 test (mask rom version only) this pin is used for ic testing. connect directly to v ss0 . chapter 2 pin functions user? manual u13029ej7v1ud 46 2.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connections of unused pins are shown in table 2-1. for each i/o circuit configuration, refer to figure 2-1. table 2-1. types of pin i/o circuits pin name i/o circuit type i/o recommended connection of unused pins p00/intp0/toff7 8-c i/o input: independently connect to v ss0 via a resistor. p01/intp1 output: leave open. p02/intp2 p03/intp3/adtrg p10/ani0 to p17/ani7 25 input connect to v dd0 or v ss0 . p20/rxd00 8-c i/o input: independently connect to v dd0 or v ss0 via a p21/txd00 5-h resistor. p22/rxd01 8-c output: leave open. p23/txd01 5-h p24/ti50/to50 8-c p25/ti51/to51 p26/ti52/to52 p30/rtp0 to p37/rtp7 5-h p40/ad0 to p47/ad7 p50 p51/sck 8-c p52/si 5-h p53/so p54/intp4/ti000/to00 p55/intp5/ti010 p56/intp6/ti001/to01 p57/intp7/ti011 p64/rd p65/wr p66/wait p67/astb to70 to to75 4 output leave open. reset 2 av dd connect to v dd0 . av ref connect to v ss0 . av ss test (mask rom version) connect directly to v ss0 . v pp (flash memory version) chapter 2 pin functions 47 user? manual u13029ej7v1ud figure 2-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics push/pull output that can become high impedance (off for both p-ch and n-ch) in type 5-h type 4 type 8-c data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pullup enable v ss0 data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pullup enable v ss0 type 25 data output disable p-ch out v dd0 n-ch v ss0 n-ch in p-ch input enable v ss0 + v ref (threshold voltage) comparator user? manual u13029ej7v1ud 48 chapter 3 cpu architecture 3.1 memory space each product in the pd780988 subseries can access a memory space of 64 kb. figures 3-1 to 3-6 show the memory maps of the respective products. cautions 1. the initial value of the internal memory size switching register (ims) is fixed (to cfh) for all the products in the pd780988 subseries, regardless of the capacity of the internal memory. therefore, set the values shown below for each microcontroller before use. pd780982: c4h pd780983: c6h pd780984: c8h pd780986: cch pd780988: cfh (no need to change the initial value because the pd780988 is set to cfh.) pd78f0988a: value corresponding to mask rom versions 2. the initial value of the internal expansion ram size switching register (ixs) is fixed (to 0ch) for all the products in the pd780988 subseries, regardless of the capacity of the internal expansion ram. therefore, set the values shown below for each microcontroller before use. pd780982, 780983, 780984: 0ch (no need to change the initial value because the pd780982, 780983, 780984 are set to 0ch). pd780986, 780988: 0ah pd78f0988a: value corresponding to mask rom versions chapter 3 cpu architecture 49 user? manual u13029ej7v1ud figure 3-1. memory map ( pd780982) 0000h data memory space general-purpose registers 32 8 bits internal rom 16,384 8 bits 3fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area reserved external memory 256 8 bits program memory space 4000h 3fffh fb00h faffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits 4100h 40ffh chapter 3 cpu architecture user? manual u13029ej7v1ud 50 figure 3-2. memory map ( pd780983) 0000h data memory space internal rom 23,775 8 bits 5fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area reserved external memory 256 8 bits program memory space 6000h 5fffh fb00h faffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits 6100h 60ffh general-purpose registers 32 8 bits chapter 3 cpu architecture 51 user? manual u13029ej7v1ud figure 3-3. memory map ( pd780984) 0000h data memory space internal rom 32,768 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area reserved external memory 256 8 bits program memory space 8000h 7fffh fb00h faffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits 8100h 80ffh general-purpose registers 32 8 bits chapter 3 cpu architecture user? manual u13029ej7v1ud 52 figure 3-4. memory map ( pd780986) internal high-speed ram 1,024 8 bits 0000h data memory space internal rom 49,152 8 bits bfffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 256 8 bits program memory space c000h bfffh fb00h faffh f800h f7ffh f400h f3ffh fee0h fedfh ff00h feffh ffffh special function registers (sfrs) 256 8 bits internal expansion ram 1,024 8 bits reserved reserved c100h c0ffh general-purpose registers 32 8 bits chapter 3 cpu architecture 53 user? manual u13029ej7v1ud figure 3-5. memory map ( pd780988) 0000h data memory space internal rom 61,440 8 bits efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area reserved reserved internal expansion ram 1,024 8 bits program memory space fb00h faffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits f000h efffh f400h f3ffh f800h f7ffh general-purpose registers 32 8 bits chapter 3 cpu architecture user? manual u13029ej7v1ud 54 figure 3-6. memory map ( pd78f0988a) 0000h data memory space flash memory 61,440 8 bits efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area reserved reserved internal expansion ram 1,024 8 bits program memory space f000h efffh fb00h faffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits f400h f3ffh f800h f7ffh general-purpose registers 32 8 bits chapter 3 cpu architecture 55 user? manual u13029ej7v1ud 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). each model in the pd780988 subseries is provided with the following internal rom (or flash memory). table 3-1. internal rom capacity part number capacity structure pd780982 mask rom 16,384 8 bits (0000h to 3fffh) pd780983 23,775 8 bits (0000h to 5fffh) pd780984 32,768 8 bits (0000h to 7fffh) pd780986 49,152 8 bits (0000h to bfffh) pd780988 61,440 8 bits (0000h to efffh) pd78f0988a flash memory 61,440 8 bits (0000h to efffh) the following areas are allocated to the internal program memory space. (1) vector table area the 64-byte area of addresses 0000h to 003fh is reserved as a vector table area. this area stores program start addresses to which the program branches when the reset signal is input or when an interrupt request is generated. of a 16-bit program start address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt source vector table address interrupt source 0000h reset input 001ch inttm001 0004h intwdt 001eh inttm011 0006h intp0 0020h intser0 0008h intp1 0022h intsr0 000ah intp2 0024h intst0 000ch intp3 0026h intsr1 000eh intp4 0028h intst1 0010h intp5 002ah inttm50 0012h intp6 002ch inttm51 0014h intp7 002eh inttm52 0016h inttm7 0030h intcsi3 0018h inttm000 0032h intad0 001ah inttm010 003eh brk instruction (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh. chapter 3 cpu architecture user? manual u13029ej7v1ud 56 (3) callf instruction entry area a subroutine can be directly called from the area of addresses 0800h to 0fffh by using a 2-byte call instruction (callf). 3.1.2 internal data memory space the pd780988 subseries are provided with the following ram. (1) internal high-speed ram the internal expansion ram is allocated to the 1024-byte area fb00h to feffh. four of these banks of general-purpose registers with eight 8-bit registers per bank are allocated to the 32-byte area fee0h to feffh. this area cannot be used as a program area in which instructions are written and executed. the internal high-speed ram can also be used as a stack memory. (2) internal expansion ram in the pd780986, 780988, and 78f0988a only, the internal expansion ram is allocated to the 1024-byte area f400h to f7ffh. the internal expansion ram can also be used as a normal data area similar to the internal high-speed ram, as well as a program area in which instructions can be written and executed. 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allocated to the area of ff00h to ffffh (refer to table 3-4 special function register list in 3.2.3 special function registers (sfrs) ). caution do not access an address to which no sfr is allocated. 3.1.4 external memory space this is an external memory space that can be accessed by setting the memory expansion mode register (mem). this space can store programs and table data, and can be assigned to peripheral devices. chapter 3 cpu architecture 57 user? manual u13029ej7v1ud 3.1.5 data memory addressing the manner of specifying the address of the instruction to be executed next or specifying the address of a register or memory to be manipulated when an instruction is executed is called addressing. the address of the instruction to be executed next is specified by the program counter (pc) (for details, refer to 3.3 instruction address addressing ). however, in consideration of operability, the pd780988 subseries is equipped with a wide range of addressing modes for memory addresses that are operational objects during instruction execution. especially, in the areas to which the data memory is assigned (addresses fb00h to ffffh), the special function registers (sfrs) and general- purpose registers can be addressed in accordance with their function. figures 3-7 to 3-12 illustrate the addressing of the data memory. for details of each addressing, refer to 3.4 operand address addressing . figure 3-7. data memory addressing ( pd780982) 0000h internal rom 16,384 8 bits short direct addressing 4100h 40ffh fb00h faffh fe20h fe1fh fee0h fedfh ff20h ff1fh ffffh ff00h feffh 4000h 3fffh external memory 256 8 bits sfr addressing direct addressing based addressing based indexed addressing special function registers (sfrs) 256 8 bits reserved internal high-speed ram 1,024 8 bits register addressing register indirect addressing general-purpose registers 32 8 bits chapter 3 cpu architecture user? manual u13029ej7v1ud 58 figure 3-8. data memory addressing ( pd780983) 0000h internal rom 23,775 8 bits short direct addressing 6000h 5fffh fb00h faffh fe20h fe1fh fee0h fedfh ff20h ff1fh ffffh ff00h feffh 6100h 60ffh external memory 256 8 bits sfr addressing direct addressing based addressing based indexed addressing special function registers (sfrs) 256 8 bits reserved internal high-speed ram 1,024 8 bits register addressing register indirect addressing general-purpose registers 32 8 bits chapter 3 cpu architecture 59 user? manual u13029ej7v1ud figure 3-9. data memory addressing ( pd780984) 0000h internal rom 32,768 8 bits short direct addressing 8000h 7fffh fb00h faffh fe20h fe1fh fee0h fedfh ff20h ff1fh ffffh ff00h feffh 8100h 80ffh external memory 256 8 bits sfr addressing direct addressing based addressing based indexed addressing special function registers (sfrs) 256 8 bits reserved internal high-speed ram 1,024 8 bits register addressing register indirect addressing general-purpose registers 32 8 bits chapter 3 cpu architecture user? manual u13029ej7v1ud 60 figure 3-10. data memory addressing ( pd780986) 0000h internal rom 49,152 8 bits internal expansion ram 1,024 8 bits short direct addressing c000h bfffh fb00h faffh f800h f7ffh f400h f3ffh fe20h fe1fh fee0h fedfh ff20h ff1fh ffffh ff00h feffh c100h c0ffh external memory 256 8 bits sfr addressing direct addressing based addressing based indexed addressing special function registers (sfrs) 256 8 bits reserved reserved internal high-speed ram 1,024 8 bits register addressing register indirect addressing general-purpose registers 32 8 bits chapter 3 cpu architecture 61 user? manual u13029ej7v1ud figure 3-11. data memory addressing ( pd780988) 0000h internal rom 61,440 8 bits short direct addressing f000h efffh fb00h faffh f800h f7ffh fe20h fe1fh fee0h fedfh ff20h ff1fh ffffh ff00h feffh f400h f3ffh internal expansion ram 1,024 8 bits sfr addressing direct addressing based addressing based indexed addressing special function registers (sfrs) 256 8 bits reserved reserved internal high-speed ram 1,024 8 bits register addressing register indirect addressing general-purpose registers 32 8 bits chapter 3 cpu architecture user? manual u13029ej7v1ud 62 figure 3-12. data memory addressing ( pd78f0988a) 0000h flash memory 61,440 8 bits internal expansion ram 1,024 8 bits short direct addressing f400h f3ffh f800h f7ffh fb00h faffh fe20h fe1fh fee0h fedfh ff20h ff1fh ffffh ff00h feffh f000h efffh sfr addressing direct addressing based addressing based indexed addressing special function registers (sfrs) 256 8 bits reserved reserved internal high-speed ram 1,024 8 bits register addressing register indirect addressing general-purpose registers 32 8 bits chapter 3 cpu architecture 63 user? manual u13029ej7v1ud 3.2 processor registers the pd780988 subseries is provided with the following processor registers. 3.2.1 control registers each of these registers has a dedicated function such as to control the program sequence, status, and stack memory. the control registers include the program counter (pc), program status word (psw), and stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register that holds the address of the program to be executed next. the contents of this register are automatically incremented according to the number of bytes of the instruction to be fetched when a normal operation is performed. when a branch instruction is executed, immediate data or the contents of a register are set to the program counter. when the reset signal is input, the value of the reset vector table at addresses 0000h and 0001h is set to the program counter. figure 3-13. program counter configuration (2) program status word (psw) the program status word is an 8-bit register consisting of flags that are set or reset as a result of instruction execution. the contents of the program status word are automatically pushed to the stack when an interrupt request is generated or when the push psw instruction is executed, and are automatically popped from the stack when the retb, reti, or pop psw instruction is executed. the contents of the program status word are set to 02h when the reset signal is input. figure 3-14. program status word configuration (a) interrupt enable flag (ie) this flag controls acknowledgement of an interrupt request by the cpu. when ie = 0, all interrupt requests except the non-maskable interrupt are disabled (di status). when ie = 1, interrupts are enabled (ei status). at this time, acknowledgement of interrupt requests is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources, and a priority specification flag. the interrupt enable flag is reset to 0 when the di instruction is executed or when an interrupt request is acknowledged, and set to 1 when the ei instruction is executed. (b) zero flag (z) this flag is set to 1 when the result of an operation performed is 0; otherwise, it is reset to 0. 15 0 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc 70 ie z rbs1 ac rbs0 0 isp cy psw chapter 3 cpu architecture user? manual u13029ej7v1ud 64 (c) register bank select flags (rbs0 and rbs1) these 2-bit flags select one of the four register banks. 2-bit information indicating the register bank selected by execution of the ?el rbn?instruction is stored in these flags. (d) auxiliary carry flag (ac) this flag is set to 1 when a carry from or a borrow to bit 3 occurs as a result of an operation; otherwise, it is reset to 0. (e) in-service priority flag (isp) this flag controls the priority of maskable vectored interrupts that can be acknowledged. when isp = 0, the vectored interrupt request whose priority is specified by the priority specification flag registers (pr0l, pr0h, pr1l) (refer to 14.3 (3) priority specification flag registers (pr0l, pr0h, pr1l) ) to be low is disabled. whether the interrupt request is actually acknowledged is controlled by the status of the interrupt enable flag (ie). (f) carry flag (cy) this flag records an overflow or underflow that occurs as the result of executing an add or subtract instruction. it also records the value shifted out when a rotate instruction is executed and functions as a bit accumulator when a bit operation instruction is executed. (3) stack pointer (sp) this is a 16-bit register that holds the first address of the stack area in the memory. only the internal high- speed ram area (fb00h to feffh) can be specified as the stack area. figure 3-15. stack pointer configuration the contents of the stack pointer are decremented when data is written (saved) to the stack memory, and incremented when data is read (restored) from the stack memory. the data saved/restored as a result of each stack operation is as shown in figures 3-16 and 3-17. caution the contents of the sp become undefined when the reset signal is input. be sure to initialize the sp before executing an instruction. 15 0 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 sp chapter 3 cpu architecture 65 user? manual u13029ej7v1ud figure 3-16. data saved to stack memory figure 3-17. data restored from stack memory interrupt, brk instructions psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair, low sp sp _ 2 sp _ 2 register pair, high call, callf, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti, retb instructions psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair, low sp sp + 2 sp register pair, high ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3 chapter 3 cpu architecture user? manual u13029ej7v1ud 66 register bank name h l d e b c a x h l d e b c a x r7 r6 r5 r4 r3 r2 r1 r0 r7 r6 r5 r4 r3 r2 r1 r0 absolute name absolute address feffh fefeh fefdh fefch fefbh fefah fef9h fef8h fef7h fef6h fef5h fef4h fef3h fef2h fef1h fef0h bank0 bank1 function name register bank name h l d e b c a x h l d e b c a x r7 r6 r5 r4 r3 r2 r1 r0 r7 r6 r5 r4 r3 r2 r1 r0 absolute name absolute address feefh feeeh feedh feech feebh feeah fee9h fee8h fee7h fee6h fee5h fee4h fee3h fee2h fee1h fee0h bank2 bank3 function name 3.2.2 general-purpose registers general-purpose registers are mapped to specific addresses of the data memory (fee0h to feffh). four banks of general-purpose registers, each consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h) are available. each register can be used as an 8-bit register. moreover, 8-bit registers can be used in pairs as 16-bit registers (ax, bc, de, and hl). each register can be described not only by a function name (x, a, c, b, e, d, l, h, ax, bc, de, or hl) but also by an absolute name (r0 to r7, rp0 to rp3). the register bank used for instruction execution is set by the cpu control instruction (sel rbn). because four register banks are provided, an efficient program can be developed by using one register bank for ordinary processing and another bank for interrupt servicing. table 3-3. absolute addresses of general-purpose registers chapter 3 cpu architecture 67 user? manual u13029ej7v1ud figure 3-18. general-purpose register configuration (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef7h fef0h feefh fee8h fee7h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef7h fef0h feefh fee8h fee7h chapter 3 cpu architecture user? manual u13029ej7v1ud 68 3.2.3 special function registers (sfrs) unlike the general-purpose registers, special function registers have their own functions and are allocated to the area of addresses ff00h to ffffh. the special function registers can also be manipulated in the same manner as the general-purpose registers by using operation, transfer, and bit manipulation instructions. the bit units in which one register is to be manipulated (1, 8, or 16 bits) differ from those of another register. the bit unit for manipulation is specified as follows: 1-bit manipulation a symbol reserved by the assembler is described as the operand (sfr.bit) of a 1-bit manipulation instruction. an address can also be specified. 8-bit manipulation a symbol reserved by the assembler is described as the operand (sfr) of an 8-bit manipulation instruction. an address can also be specified. 16-bit manipulation a symbol reserved by the assembler is described as the operand (sfrp) of a 16-bit manipulation instruction. when specifying an address, describe an even address. table 3-4 lists the special function registers. the meanings of the symbols in this table are as follows: symbol these symbols indicate the addresses of the special function registers. they are reserved words for the ra78k0 and defined by header file sfrbit.h for the cc78k0. these symbols can be described as the operands of instructions when the ra78k0, id78k0-ns, id78k0, and sm78k0 are used. r/w indicates whether the special function register in question can be read or written. r/w: read/write r: read only w: write only bit unit for manipulation ?indicates the manipulatable bit unit (1, 8, or 16). ?indicates the bit units for which manipulation is not possible. after reset indicates the status of the special function register when the reset signal is input. chapter 3 cpu architecture 69 user? manual u13029ej7v1ud table 3-4. special function register list (1/4) address special function register (sfr) name symbol r/w bit unit for manipulation after reset 1 bit 8 bits 16 bits ff00h port 0 p0 r/w ? 00h ff01h port 1 p1 r ? ff02h port 2 p2 r/w ? ff03h port 3 p3 ? ff04h port 4 p4 ? ff05h port 5 p5 ? ff06h port 6 p6 ? ff07h 8-bit timer counter 52 tm52 r ff08h 10-bit buffer register 0 bfcm0 bfcm0l r/w r/w ? 0000h ff09h ff0ah 10-bit buffer register 1 bfcm1 bfcm1l r/w r/w ? ff0bh ff0ch 10-bit buffer register 2 bfcm2 bfcm2l r/w r/w ? ff0dh ff0eh 10-bit buffer register 3 bfcm3 bfcm3l r/w r/w ? 00ffh ff0fh ff10h 16-bit timer counter 00 tm00 r 0000h ff11h ff12h 16-bit timer counter 01 tm01 ff13h ff14h 8-bit timer counter 50 tm5 tm50 ? 00h ff15h 8-bit timer counter 51 tm51 ff16h 8-bit compare register 50 cr5 cr50 r/w ? undefined ff17h 8-bit compare register 51 cr51 ff18h a/d conversion result register 0 adcr0 r ff19h ff1ah transmit shift register 0 txs00 w ffh receive buffer register 0 rxb00 r ff1bh transmit shift register 1 txs01 w receive buffer register 1 rxb01 r ff1fh serial i/o shift register 3 sio3 r/w undefined ff20h port mode register 0 pm0 ? ffh ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ff24h port mode register 4 pm4 ? ff25h port mode register 5 pm5 ? ff26h port mode register 6 pm6 ? chapter 3 cpu architecture user? manual u13029ej7v1ud 70 table 3-4. special function register list (2/4) address special function register (sfr) name symbol r/w bit unit for manipulation after reset 1 bit 8 bits 16 bits ff30h pull-up resistor option register 0 pu0 r/w ? 00h ff32h pull-up resistor option register 2 pu2 ? ff33h pull-up resistor option register 3 pu3 ? ff34h pull-up resistor option register 4 pu4 ? ff35h pull-up resistor option register 5 pu5 ? ff36h pull-up resistor option register 6 pu6 ? ff42h watchdog timer clock select register wdcs ff47h memory extension mode register mem w ff48h external interrupt rising edge enable register egp r/w ? ff49h external interrupt falling edge enable register egn ? ff60h 16-bit timer mode control register 00 tmc00 ? ff61h prescaler mode register 00 prm00 ff62h capture/compare control register 00 crc00 ? ff63h timer output control register 00 toc00 ? ff64h 16-bit capture/compare register 000 cr000 undefined ff65h ff66h 16-bit capture/compare register 010 cr010 ff67h ff68h 16-bit timer mode control register 01 tmc01 ? 00h ff69h prescaler mode register 01 prm01 ff6ah capture/compare control register 01 crc01 ? ff6bh timer output control register 01 toc01 ? ff6ch 16-bit capture/compare register 001 cr001 undefined ff6dh ff6eh 16-bit capture/compare register 011 cr011 ff6fh ff70h 8-bit timer mode control register 50 tmc50 ? 00h ff71h timer clock select register 50 tcl50 ff74h 8-bit timer mode control register 51 tmc51 ? ff75h timer clock select register 51 tcl51 ff78h 8-bit timer mode control register 52 tmc52 ? ff79h timer clock select register 52 tcl52 ff7ah 8-bit compare register 52 cr52 undefined ff7ch external interrupt rising edge enable register 5 egp5 ? 00h ff7dh external interrupt falling edge enable register 5 egn5 ? ff80h a/d converter mode register 0 adm0 ? ff81h analog input channel specification register 0 ads0 ff84h real-time output buffer register 0l rtbl00 ? ff85h real-time output buffer register 0h rtbh00 ? chapter 3 cpu architecture 71 user? manual u13029ej7v1ud address special function register (sfr) name symbol r/w bit unit for manipulation after reset 1 bit 8 bits 16 bits ff86h real-time output port mode register 0 rtpm00 r/w ? 00h ff87h real-time output port control register 0 rtpc00 ? ff89h flash programming mode control register flpmc ? 08h note 1 ff90h inverter timer control register 7 tmc7 ? 00h ff91h inverter timer mode register 7 tmm7 ? ff92h 10-bit compare register 0 cm0 r/w r/w ? 0000h ff93h ff94h 10-bit compare register 1 cm1 r/w r/w ? ff95h ff96h 10-bit compare register 2 cm2 r/w r/w ? ff97h ff98h 10-bit compare register 3 cm3 r/w r/w ? 00ffh ff99h ff9ah dead time reload register dtime w ffh ff9ch real-time output buffer register 1l rtbl01 r/w ? 00h ff9dh real-time output buffer register 1h rtbh01 ? ff9eh real-time output port mode register 1 rtpm01 ? ff9fh real-time output port control register 1 rtpc01 ? ffa0h asynchronous serial interface mode register 0 asim00 ? ffa1h asynchronous serial interface status register 0 asis00 r ffa2h baud rate generator control register 0 brgc00 r/w ffa8h asynchronous serial interface mode register 1 asim01 ? ffa9h asynchronous serial interface status register 1 asis01 r ffaah baud rate generator control register 1 brgc01 r/w ffb0h serial operation mode register 3 csim3 ? ffb8h dc control register 0 dcctl0 ? ffbch dc control register 1 dcctl1 ? ffd0h external access area note 2 ? undefined to ffdfh ffe0h interrupt request flag register 0l if0l if0 ?? 00h ffe1h interrupt request flag register 0h if0h ? ffe2h interrupt request flag register 1l if1l ? ffe4h interrupt mask flag register 0l mk0l mk0 ?? ffh ffe5h interrupt mask flag register 0h mk0h ? ffe6h interrupt mask flag register 1l mk1l ? ffe8h priority specification flag register 0l pr0l pr0 ?? table 3-4. special function register list (3/4) notes 1. bit 2 changes according to the voltage level of v pp . 2. the external access area cannot be accessed in the sfr addressing mode. access this area with direct addressing. chapter 3 cpu architecture user? manual u13029ej7v1ud 72 address special function register (sfr) name symbol r/w bit unit for manipulation after reset 1 bit 8 bits 16 bits ffe9h priority specification flag register 0h pr0h pr0 r/w ?? ffh ffeah priority specification flag register 1l pr1l ? fff0h memory size switching register ims cfh note 1 fff4h internal expansion ram size switching register ixs 0ch note 2 fff8h memory extension wait setting register mm 10h fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time select register osts 04h fffbh processor clock control register pcc ? notes 1. the initial value is cfh, but set and operate each microcontroller with the values shown below. pd780982: c4h pd780983: c6h pd780984: c8h pd780986: cch pd780988: cfh (no need to change the initial value because the pd780988 is set to cfh). pd78f0988a: value corresponding to those of mask rom versions 2. the initial value is 0ch, but set and operate each microcontroller with the values shown below. pd780982, 780983, 780984: 0ch (no need to change the initial value because the pd780982, 780983, 780984 are set to 0ch). pd780986, 780988: 0ah pd78f0988a: value corresponding to mask rom versions table 3-4. special function register list (4/4) chapter 3 cpu architecture 73 user? manual u13029ej7v1ud 3.3 instruction address addressing an instruction address is determined by the contents of the program counter (pc). the contents of the pc are usually automatically incremented by the number of bytes of the instruction to be fetched (by 1 per byte) every time an instruction is executed. when an instruction that causes program execution to branch is performed, the address information of the branch destination is set to the pc by means of the following addressing (for details of each instruction, refer to 78k/0 series user? manual instructions (u12326e) ). 3.3.1 relative addressing [function] the 8-bit immediate data (displacement value: jdisp8) of the instruction code is added to the first address of the next instruction, the resultant sum is transferred to the program counter (pc), and program execution branches. the displacement value is treated as signed 2? complement data (?28 to +127), and bit 7 serves as a sign bit. in other words, relative addressing consists of relative branching from the first address of the following instruction to the ?28 to +127 range. this addressing is used when the ?r $addr16?instruction or conditional branch instruction is executed. [operation] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc holds first address of instruction next to br instruction. ... chapter 3 cpu architecture user? manual u13029ej7v1ud 74 3.3.2 immediate addressing [function] the immediate data in an instruction word is transferred to the program counter (pc), and program execution branches. this addressing is used when the ?all !addr16? ?r !addr16? or ?allf !addr11?instruction is executed. the call !addr16 and br !addr16 instructions allow the program to branch to the entire memory space. the callf !addr11 instruction allows the program to branch to the 0800h to 0fffh area. [operation] when the ?all !addr16?or ?r !addr16?instruction is executed when the ?allf !addr11?instruction is executed 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10 to 8 11 10 00001 643 callf fa 7 to 0 chapter 3 cpu architecture 75 user? manual u13029ej7v1ud 3.3.3 table indirect addressing [function] the contents of a specific location table (branch destination address) addressed by the immediate data of bits 1 to 5 of an instruction code are transferred to the program counter (pc), and program execution branches. this addressing is used when the ?allt [addr5]?instruction is executed. this instruction references the addresses stored in the memory table from 40h to 7fh, and allows the program to branch to the entire memory space. [operation] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 1 11 76 5 10 ta 4 to 0 instruction code chapter 3 cpu architecture user? manual u13029ej7v1ud 76 3.3.4 register addressing [function] the contents of the register pair (ax) specified by an instruction word are transferred to the program counter (pc), and program execution branches. this addressing is used when the ?r ax?instruction is executed. [operation] 70 rp 07 ax 15 0 pc 87 chapter 3 cpu architecture 77 user? manual u13029ej7v1ud 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] this addressing is used to automatically (implicitly) address a register that functions as an accumulator (a or ax) in the general-purpose register area. the instruction words of the pd780988 subseries that use implied addressing are as follows. instruction register specified by implied addressing mulu register a to store multiplicand and register ax to store product divuw register ax to store dividend and quotient adjba/adjbs register a to store numeric value subject to decimal adjustment ror4/rol4 register a to store digit data subject to digit rotation [operand format] no specific operand format is used because the operand format is automatically determined by the instruction. [example] mulu x the product between registers a and x is stored in register ax as a result of executing the multiply instruction of 8 bits 8 bits. in this operation, registers a and ax are specified by implied addressing. chapter 3 cpu architecture user? manual u13029ej7v1ud 78 3.4.2 register addressing [function] this addressing is used to access a general-purpose register as an operand. the general-purpose register to be accessed is specified by the register bank select flags (rbs0 and rbs1) and with the register specification code (rn and rpn) in an instruction code. register addressing is used when an instruction that has the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified by 3 bits in the instruction code. [operand format] representation description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described not only by a function name (x, a, c, b, e, d, l, h, ax, bc, de, or hl) but also by an absolute name (r0 to r7, rp0 to rp3). [example] mov a, c; to select c register as r instruction code 01100010 incw de; to select de register pair as rp register specification code instruction code 10000100 register specification code chapter 3 cpu architecture 79 user? manual u13029ej7v1ud 3.4.3 direct addressing [function] the addressing is used to directly address the memory indicated by the immediate data in an instruction word. [operand format] representation description addr16 label or 16-bit immediate data [example] mov a, !0fe00h; to specify fe00h as !addr16 instruction code 10001110 op code 00000000 00h 11111110 feh [operation] memory 0 7 addr16 (lower) addr16 (higher) op code chapter 3 cpu architecture user? manual u13029ej7v1ud 80 3.4.4 short direct addressing [function] this addressing directly addresses a memory area to be manipulated from a fixed space by using the 8-bit data in an instruction word. this addressing is applicable to the fixed 256-byte space of fe20h to ff1fh. the internal high-speed ram is mapped to addresses fe20h to feffh, and special function registers (sfrs) are mapped to addresses ff00h to ff1fh. the sfr area (ff00h to ff1fh) to which short direct addressing is applied is a part of the entire sfr area. ports that are frequently accessed in the program, and compare and capture registers of timer/event counters are mapped to the sfr area. these sfrs can be manipulated with a few bytes and clocks. bit 8 of the effective address is 0 if the 8-bit immediate data is in the range of 20h to ffh, and 1 if the data is in the range of 00h to 1fh. refer to [operation] . [operand format] representation description saddr label or immediate data fe20h to ff1fh saddrp label or immediate data fe20h to ff1fh (even address only) 15 0 effective address 8 7 0 1 op code saddr-offset 111111 short direct memory when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 [example] mov 0fe30h, #50h; to specify fe30h as saddr and 50h as immediate data instruction code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) [operation] chapter 3 cpu architecture 81 user? manual u13029ej7v1ud 3.4.5 special function register (sfr) addressing [function] this addressing is to address special function registers (sfrs) mapped to the memory by using the 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte space of ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped to the area of ff00h to ff1fh can also be accessed by means of short direct addressing. [operand format] representation description sfr special function register name sfrp name of special function register that can be manipulated in 16-bit units (even address only) [example] mov pm0, a; to select pm0 (ff20h) as sfr instruction code 11110110 op code 00100000 20h (sfr-offset) [operation] 15 0 effective address 87 7 0 1 op code sfr-offset 111111 sfr 1 chapter 3 cpu architecture user? manual u13029ej7v1ud 82 3.4.6 register indirect addressing [function] this addressing is used to address memory using the contents of a specified register pair as an operand. the register pair to be accessed is specified by the register bank select flags (rbs0 and rbs1) and the register pair specification code in an instruction code. this addressing can address the entire memory space. [operand format] representation description [de], [hl] [example] mov a, [de]; to select [de] as register pair instruction code 10000101 [operation] 15 0 de 87 de 7 0 0 7 a memory the contents of the memory addressed are transferred the memory address specified with the register pair de chapter 3 cpu architecture 83 user? manual u13029ej7v1ud 3.4.7 based addressing [function] this addressing is used to address the memory by using the result of adding 8-bit immediate data to the contents of the hl register pair used as a base register. the hl register pair to be accessed is in the register bank specified by the register bank select flags (rbs0 and rbs1). the addition is executed by extending the offset data to 16 bits as a positive number. a carry from the 16th bit is ignored. this addressing can address the entire memory space. [operand format] representation description [hl + byte] [example] mov a, [hl + 10h]; to specify 10h as byte instruction code 10101110 00010000 chapter 3 cpu architecture user? manual u13029ej7v1ud 84 3.4.8 based indexed addressing [function] this addressing is used to address the memory by using the result of adding the contents of the b or c register specified in the instruction word to the contents of the hl register used as a base register. the hl, b, and c registers accessed are in the register bank specified by the register bank select flags (rbs0 and rbs1). the addition is executed with the contents of the b or c register extended to 16 bits as a positive number. a carry from the 16th bit is ignored. this addressing can address the entire memory space. [operand format] representation description [hl + b], [hl + c] [example] when mov a, [hl + b] instruction code 10101011 3.4.9 stack addressing [function] this addressing is used to indirectly address the stack area by using the contents of the stack pointer (sp). this addressing is automatically used to save/restore register contents when the push, pop, subroutine call, or return instruction is executed, or when an interrupt request is generated. stack addressing can access the internal high-speed ram area only. [example] when push de is executed instruction code 10110101 85 user? manual u13029ej7v1ud chapter 4 port functions 4.1 function of ports the pd780988 subseries is provided with eight input port pins and 39 i/o port pins. figure 4-1 shows these port pins. each port can be manipulated in 1-bit or 8-bit units and controlled in various ways. moreover, some port pins also serve as the i/o pins of the internal hardware. figure 4-1. types of ports port 4 port 0 port 5 port 6 port 1 8 port 2 p00 p40 p47 p10 to p17 p50 p57 p64 p67 p03 p30 p37 port 3 p26 p20 chapter 4 port functions user? manual u13029ej7v1ud 86 table 4-1. port functions p00 p01 p02 p03 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p30 to p37 p40 to p47 p50 p51 p52 p53 p54 p55 p56 p57 p64 p65 p66 p67 alternate function intp0/toff7 intp1 intp2 intp3/adtrg ani0 to ani7 rxd00 txd00 rxd01 txd01 ti50/to50 ti51/to51 ti52/to52 rtp0 to rtp7 ad0 to ad7 sck si so intp4/ti000/to00 intp5/ti010 intp6/ti001/to01 intp7/ti011 rd wr wait astb function port 0 port 1 port 2 port 3 port 4 port 5 port 6 4-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. 8-bit input-only port 7-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. 8-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. 8-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. 8-bit i/o port leds can be driven directly. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. 4-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. pin name chapter 4 port functions 87 user? manual u13029ej7v1ud 4.2 configuration of ports a port consists of the following hardware. table 4-2. port configuration item configuration control registers port mode register (pm0, pm2 to pm6) pull-up resistor option register (pu0, pu2 to pu6) ports total 47 input 8 i/o 39 pull-up resistors 39 (software control) 4.2.1 port 0 this is a 4-bit i/o port with output latches. port 0 can be set in the input or output mode in 1-bit units via port mode register 0 (pm0). when using port 0, internal pull-up resistors can be connected in 1-bit units by using pull-up resistor option register 0 (pu0). alternate functions include external interrupt request input, external input to stop timer output, and an external trigger signal for the a/d converter. reset input sets port 0 to input mode. figure 4-2 shows the block diagram of port 0. caution because port 0 is also used as an external interrupt request input, an interrupt request flag is set when the port is set in the output mode and its output level is changed. when using port 0 in the output mode, therefore, set the interrupt mask flag to 1. chapter 4 port functions user? manual u13029ej7v1ud 88 figure 4-2. block diagram of p00 to p03 pu: pull-up resistor option register pm: port mode register rd: read signal of port 0 wr: write signal of port 0 4.2.2 port 1 this is an 8-bit input port. alternate functions include a/d converter analog input. figure 4-3 shows the block diagram of port 1. figure 4-3. block diagram of p10 to p17 p10/ani0 to p17/ani7 rd internal bus p-ch wr pm wr port rd wr pu v dd p00/intp0/toff7, p01/intp1, p02/intp2, p03/intp3/adtrg selector pu00 to pu03 output latch (p00 to p03) pm00 to pm03 internal bus chapter 4 port functions 89 user? manual u13029ej7v1ud 4.2.3 port 2 this is a 7-bit i/o port with output latches. port 2 can be set in the input or output mode in 1-bit units via port mode register 2 (pm2). when using port 2, internal pull-up resistors can be connected in 1-bit units by using pull-up resistor option register 2 (pu2). alternate functions include serial interface data i/o and timer i/o. reset input sets port 2 to input mode. figure 4-4 shows the block diagram of port 2. caution when performing transmission using the serial interface or timer output, set the pins to be used to output mode, and set the output latch to 0. when performing reception or timer input, set the pins to be used to input mode. figure 4-4. block diagram of p20 to p26 pu: pull-up resistor option register pm: port mode register rd: read signal of port 2 wr: write signal of port 2 p-ch wr pm wr port rd wr pu v dd p20/rxd00, p21/txd00, p22/rxd01, p23/txd01, p24/ti50/to50, p25/ti51/to51, p26/ti52/to52 selector pu20 to pu26 output latch (p20 to p26) pm20 to pm26 alternate function internal bus chapter 4 port functions user? manual u13029ej7v1ud 90 4.2.4 port 3 this is an 8-bit i/o port with output latches. port 3 can be set in the input or output mode in 1-bit units via port mode register 3 (pm3). when using port 3, internal pull-up resistors can be connected in 1-bit units by using pull- up resistor option register 3 (pu3). alternate functions include use as a real-time output port. reset input sets port 3 to input mode. figure 4-5 shows the block diagram of port 3. figure 4-5. block diagram of p30 to p37 p-ch wr pm wr port rd wr pu v dd p30/rtp0 to p37/rtp7 selector pu30 to pu37 output latch (p30 to p37) pm30 to pm37 alternate function internal bus pu: pull-up resistor option register pm: port mode register rd: read signal of port 3 wr: write signal of port 3 chapter 4 port functions 91 user? manual u13029ej7v1ud 4.2.5 port 4 this is an 8-bit i/o port with output latches. port 4 can be set in the input or output mode in 1-bit units via port mode register 4 (pm4). when using port 4, internal pull-up resistors can be connected in 1-bit units by using pull- up resistor option register 4 (pu4). alternate functions include an address/data bus function that is used in the external memory expansion mode. reset input sets port 4 to input mode. figure 4-6 shows the block diagram of port 4. figure 4-6. block diagram of p40 to p47 pu: pull-up resistor option register pm: port mode register rd: read signal of port 4 wr: write signal of port 4 p-ch wr pm wr port rd wr pu v dd p40/ad0 to p47/ad7 selector pu40 to pu47 output latch (p40 to p47) pm40 to pm47 internal bus chapter 4 port functions user? manual u13029ej7v1ud 92 4.2.6 port 5 this is an 8-bit i/o port with output latches. port 5 can be set in the input or output mode in 1-bit units via port mode register 5 (pm5). when using port 5, internal pull-up resistors can be connected in 1-bit units by using pull- up resistor option register 5 (pu5). port 5 can directly drive leds. alternate functions include serial interface clock and data i/o, timer i/o, and external interrupt request input. reset input sets port 5 to input mode. figures 4-7 and 4-8 show the block diagram of port 5. cautions 1. when performing transmission using the serial interface or timer output, set the pins to be used to output mode, and set the output latch to 0. when performing reception or timer input, set the pins to be used to input mode. 2. because pins p54 to p57 are also used as external interrupt request input pins, an interrupt request flag is set when the port is set in the output mode and its output level is changed. when using the output mode, therefore, set the interrupt mask flag to 1. figure 4-7. block diagram of p50 p-ch wr pm wr port rd wr pu v dd p50 selector pu50 output latch (p50) pm50 internal bus pu: pull-up resistor option register pm: port mode register rd: read signal of port 5 wr: write signal of port 5 chapter 4 port functions 93 user? manual u13029ej7v1ud figure 4-8. block diagram of p51 to p57 p-ch wr pm wr port rd wr pu v dd p51/sck, p52/si, p53/so, p54/intp4/ti000/to00, p55/intp5/ti010, p56/intp6/ti001/to01, p57/intp7/ti011 selector pu51 to pu57 output latch (p51 to p57) pm51 to pm57 alternate function internal bus pu: pull-up resistor option register pm: port mode register rd: read signal of port 5 wr: write signal of port 5 chapter 4 port functions user? manual u13029ej7v1ud 94 4.2.7 port 6 this is a 4-bit i/o port with output latches. port 6 can be set in the input or output mode in 1-bit units via port mode register 6 (pm6). when using port 6, internal pull-up resistors can be connected in 1-bit units by using pull-up resistor option register 6 (pu6). alternate functions include a control signal output function in the external memory expansion mode. reset input sets port 6 to input mode. figure 4-9 shows the block diagram of port 6. caution p66 can be used as an i/o port pin when no external wait state is used in the external memory expansion mode. figure 4-9. block diagram of p64 to p67 wr pm wr port rd p64/rd, p65/wr, p66/wait, p67/astb selector output latch (p64 to p67) pm64 to pm67 p-ch wr pu v dd pu64 to pu67 internal bus pu: pull-up resistor option register pm: port mode register rd: read signal of port 6 wr: write signal of port 6 chapter 4 port functions 95 user? manual u13029ej7v1ud 4.3 registers controlling port functions the following two types of registers control the ports. port mode registers (pm0, pm2, pm3, pm4, pm5, pm6) pull-up resistor option registers (pu0, pu2, pu3, pu4, pu5, pu6) (1) port mode registers (pm0, pm2, pm3, pm4, pm5, pm6) these registers set the corresponding ports in the input or output mode in 1-bit units. pm0, pm2, pm3, pm4, pm5, and pm6 are manipulated by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. cautions 1. because port 0 and pins p54 to p57 are also used as external interrupt request input pins, interrupt request flags are set when the output mode of the port function is specified and the output level is changed. to use this port in the output mode, therefore, set the interrupt mask flags to 1 in advance. 2. since pull-up resistors will not be disconnected even if ports 0 and 2 to 6 are set to output mode, set corresponding pull-up resistor option registers to 0 when those ports are used in output mode. 3. when a port pin that has an alternate function serves as an alternate function output pin, set its output latch to 0. figure 4-10. format of port mode register pm0 pm4 pm2 11 11 pm03 pm02 pm01 pm00 76543210 symbol pm3 pm6 pm5 pmmn selects i/o mode of pmn pin (m = 0: n = 0 to 3) (m = 2: n = 0 to 6) (m = 3, 4, 5: n = 0 to 7) (m = 6: n = 4 to 7) 0 1 output mode (output buffer on) input mode (output buffer off) ff20h ff24h ff22h ff23h ff25h ff26h ffh ffh ffh ffh ffh ffh r/w r/w r/w r/w r/w r/w address after reset r/w pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 pm67 pm66 pm65 pm64 1 1 1 1 chapter 4 port functions user? manual u13029ej7v1ud 96 00 00 pu02 pu01 pu00 pu0 pumn selects internal pull-up resistor of pmn pin (m = 0: n = 0 to 3) (m = 2: n = 0 to 6) (m = 3, 4, 5: n = 0 to 7) (m = 6: n = 4 to 7) 0 1 on-chip pull-up resistor is not used on-chip pull-up resistor is used ff30h 00h r/w 54 symbol address after reset r/w pu03 0 pu26 pu25 pu24 pu22 pu21 pu20 pu2 ff32h 00h r/w pu23 pu36 pu35 pu34 pu32 pu31 pu30 pu3 ff33h 00h r/w pu33 pu47 pu37 pu46 pu45 pu44 pu42 pu41 pu40 pu4 ff34h 00h r/w pu43 pu57 pu56 pu55 pu54 pu52 pu51 pu50 pu5 ff35h 00h r/w pu53 pu67 pu66 pu65 pu64 0 0 0 pu6 ff36h 00h r/w 0 76 32 0 1 (2) pull-up resistor option registers (pu0, pu2, pu3, pu4, pu5, pu6) these registers set whether the internal pull-up resistor is connected to each port. by setting pu0 and pu2 to pu6, on-chip pull-up resistors corresponding to bits in pu0 and pu2 to pu6 can be used. pu0, pu2 to pu6 are individually set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. cautions 1. port 1 is not provided with an on-chip pull-up resistor. 2. when pum is set to 1, an on-chip pull-up resistor is connected regardless of whether the mode is input/output mode or external expansion mode. accordingly, when using the port in output or external expansion mode, set the corresponding bit of pum to 0 (m = 0, 2 to 6). figure 4-11. format of pull-up resistor option register chapter 4 port functions 97 user? manual u13029ej7v1ud 4.4 operation of port functions the operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output latch of a port by using a transfer instruction. the contents of the output latch can be output from the pins of the port. data once written to the output latch is retained until new data is written to the output latch. (2) in input mode a value can be written to the output latch by using a transfer instruction. however, the status of the port pin is not changed because the output buffer is off. data once written to the output latch is retained until new data is written to the output latch. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 reading from i/o port (1) in output mode the contents of the output latch can be read by using a transfer instruction. the contents of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 4.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed on the contents of the output latch. the result of the operation is written to the output latch. the contents of the output latch are output from the port pins. data once written to the output latch is retained until new data is written to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. user? manual u13029ej7v1ud 98 chapter 5 clock generator 5.1 function of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. oscillation can be stopped by executing the stop instruction. ? expanded-specification products the system oscillator oscillates a frequency of 1.0 to 12.0 mhz. ? conventional products the system oscillator oscillates a frequency of 1.0 to 8.38 mhz. 5.2 configuration of clock generator the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control register processor clock control register (pcc) oscillator system clock oscillator figure 5-1. clock generator block diagram system clock oscillator prescaler prescaler clock to peripheral hardware standby controller wait controller cpu clock (f cpu ) selector f x 2 f x 2 2 f x 2 3 f x 2 4 stop f x x1 x2 chapter 5 clock generator 99 user? manual u13029ej7v1ud 5.3 register controlling clock generator the clock generator is controlled by the processor clock control register (pcc). this register selects the cpu clock. pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 04h. figure 5-2. format of processor clock control register caution be sure to clear bits 3 to 7 to 0. remark f x : system clock oscillation frequency the fastest instruction of the pd780988 subseries is executed in two cpu clocks. therefore, the relationship between the cpu clock (f cpu ) and the minimum instruction execution time is as shown in table 5-2. table 5-2. relationship between cpu clock and minimum instruction execution time cpu clock (f cpu ) minimum instruction execution time: 2/f cpu at f x = 12 mhz note at f x = 8.38 mhz f x 0.166 s 0.238 s f x /2 0.33 s 0.48 s f x /2 2 0.66 s 0.96 s f x /2 3 1.3 s 1.9 s f x /2 4 2.6 s 3.8 s note expanded-specification products only. remark f x : system clock oscillation frequency 00 00 pcc2 pcc1 pcc0 pcc fffbh 04h r/w 65 4 symbol address after reset r/w 0 7320 1 0 0f x /2 pcc2 selects cpu ciock (f cpu ) pcc1 pcc0 0 0 0 1 0 0 1 1 0 1 100 f x /2 2 f x /2 3 f x /2 4 f x setting prohibited other than above chapter 5 clock generator user? manual u13029ej7v1ud 100 5.4 system clock oscillators 5.4.1 system clock oscillator the system clock oscillator is oscillated by the crystal or ceramic resonator (12 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in this case, input the clock signal to the x1 pin, and input the inverted signal to the x2 pin. figure 5-3 shows the external circuit of the system clock oscillator. figure 5-3. external circuit of system clock oscillator (a) crystal or ceramic oscillation (b) external clock cautions 1. the stop instruction cannot be executed when the external clock is input. this is because if the stop instruction is executed, the system clock operation is stopped, and the x2 pin is pulled up to v dd1 . 2. when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. figure 5-4 shows examples of incorrect resonator connection. x2 x1 v ss1 crystal or ceramic resonator x2 x1 external clock chapter 5 clock generator 101 user? manual u13029ej7v1ud figure 5-4. examples of incorrect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss1 x1 x2 v ss1 x1 pnm x2 v ss1 x1 x2 v ss1 x1 pnm v dd abc high current high current (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) chapter 5 clock generator user? manual u13029ej7v1ud 102 figure 5-4. examples of incorrect resonator connection (2/2) (e) signal is fetched x2 v ss1 x1 5.4.2 divider the divider divides the output of the system clock oscillator (f x ) to generate various clocks. chapter 5 clock generator 103 user? manual u13029ej7v1ud 5.5 operation of clock generator the clock generator generates the following clocks and controls the operation modes of the cpu, such as the standby mode. system clock f x cpu clock f cpu clock to peripheral hardware the operation of the clock generator is determined by the processor clock control register (pcc), as follows. (a) the slowest mode (2.6 s @ 12 mhz operation, 3.8 s @ 8.38 mhz operation) of the system clock is selected when the reset signal is generated (pcc = 04h). while a low level is input to the reset pin, oscillation of the system clock is stopped. (b) five types of minimum instruction execution time (0.166 s, 0.33 s, 0.66 s, 1.3 s, and 2.6 s @ 12 mhz operation/0.238 s, 0.48 s, 0.96 s, 1.9 s, and 3.8 s @ 8.38 mhz operation) can be selected via a pcc setting when the system clock is in the selected state. (c) two standby modes, stop and halt, can be used. (d) the clock to the peripheral hardware is supplied by dividing the system clock. therefore, the other peripheral hardware is stopped when the system clock is stopped (except, however, the external clock input operation). chapter 5 clock generator user? manual u13029ej7v1ud 104 5.6 changing setting of cpu clock 5.6.1 time required for switching cpu clock the cpu clock can be selected by using bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc). actually, the specified clock is not selected immediately after the setting of pcc has been changed, and the old clock is used for the duration of several instructions after that (refer to table 5-3 ). table 5-3. maximum time required for switching cpu clock remark one instruction is the minimum instruction execution time of the cpu clock before switching. set value before switching set value after switching pcc1 pcc2 pcc0 16 instructions 16 instructions 16 instructions 16 instructions 8 instructions 8 instructions 8 instructions 8 instructions 4 instructions 4 instructions 4 instructions 4 instructions 2 instructions 2 instructions 2 instructions 2 instructions 1 instruction 1 instruction 1 instruction 1 instruction 0 0 0 0 1 0 0 0 pcc2 pcc1 pcc0 0 0 0 1 1 1 0 0 0 1 pcc0 pcc1 pcc2 00 1 pcc1 pcc2 01 pcc0 0 pcc1 pcc2 01 pcc0 1 pcc1 pcc2 10 pcc0 0 chapter 5 clock generator 105 user? manual u13029ej7v1ud 5.6.2 switching cpu clock the following figure illustrates how the cpu clock is switched. figure 5-5. switching between system clock and cpu clock <1> the cpu is reset when the reset pin is made low on power application. the effect of resetting is released when the reset pin is later made high, and the system clock starts oscillating. at this time, the time during which oscillation stabilizes (2 17 /f x ) is automatically secured. after that, the cpu starts instruction execution at the slowest speed of the system clock (2.6 s @ 12 mhz operation, 3.8 s @ 8.38 mhz operation). <2> after the time during which the v dd1 voltage rises to the level at which the cpu can operate at the highest speed has elapsed, processor clock control register (pcc) is rewritten so that the highest speed can be selected. v dd1 reset cpu clock wait (10.9 ms @ 12 mhz operation) internal reset operation lowest- speed operation highest-speed operation user? manual u13029ej7v1ud 106 chapter 6 16-bit timer/event counter 6.1 outline of 16-bit timer/event counter a 16-bit timer/event counter can be used as an interval timer, for ppg output, pulse width measurement (infrared remote control receive function), as an external event counter, or for square-wave output of any frequency. 6.2 function of 16-bit timer/event counter the 16-bit timer/event counters have the following functions. interval timer ppg output pulse width measurement external event counter square-wave output (1) interval timer tm0n generates interrupt requests at the preset time interval. (2) ppg output tm0n can output a square wave whose frequency and output pulse can be set freely. (3) pulse width measurement tm0n can measure the pulse width of an externally input signal. (4) external event counter tm0n can measure the number of pulses of an externally input signal. (5) square-wave output tm0n can output a square wave with any selected frequency. chapter 6 16-bit timer/event counter 107 user? manual u13029ej7v1ud 6.3 configuration of 16-bit timer/event counter a 16-bit timer/event counter includes the following hardware. table 6-1. configuration of 16-bit timer/event counter item configuration timer register 16-bit timer counter 0n (tm0n) register 16-bit capture/compare register 00n, 01n (cr00n, cr01n) timer output to0n control register 16-bit timer mode control register 0n (tmc0n) capture/compare control register 0n (crc0n) timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) port mode register 5 (pm5) note note refer to figure 4-8 block diagram of p51 to p57 . remark n = 0, 1 figure 6-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/p55/intp5 f x f x /2 2 f x /2 5 f x /2 4 ti000/p54/ intp4/to00 prescaler mode register 00 (prm00) 2 noise elimi- nator noise elimi- nator prm001 prm000 crc002 16-bit capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) selector selector noise elimi- nator crc002 crc001 crc000 16-bit capture/compare register 000 (cr000) inttm000 intp5 to00/p54/ intp4/ti000 inttm010 intp4 output controller timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 clear chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 108 figure 6-2. block diagram of 16-bit timer/event counter 01 (1) 16-bit timer counter 00, 01 (tm00, tm01) tm00 and tm01 are 16-bit read-only registers that count the count pulses. the counter is incremented in synchronization with the rising edge of the input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases. <1> at reset input <2> if tmc0n3 and tmc0n2 are cleared <3> if the valid edge of ti00n is input in the clear & start mode entered by inputting the valid edge of ti00n <4> if tm0n and cr00n match in the clear & start mode entered on a match between tm0n and cr00n remark n = 0, 1 (2) 16-bit capture/compare register 000, 001 (cr000, cr001) cr000 and cr001 are 16-bit registers that have the functions of both a capture register and a compare register. whether to be used as a capture register or as a compare register is set by bit 0 (crc0n0) of capture/compare control register 0n (crc0n). internal bus capture/compare control register 01 (crc01) ti011/p57/intp7 f x f x /2 2 f x /2 5 f x /2 4 ti001/p56/ intp6/to01 prescaler mode register 01 (prm01) 2 noise elimi- nator noise elimi- nator prm011prm010 crc012 16-bit capture/compare register 011 (cr011) match match 16-bit timer counter 01 (tm01) selector selector noise elimi- nator crc012 crc011 crc010 16-bit capture/compare register 001 (cr001) inttm001 intp7 to01/p56/ intp6/ti001 inttm011 intp6 timer output control register 01 (toc01) 16-bit timer mode control register 01 (tmc01) internal bus tmc013 tmc012 tmc011 ovf01 toc014 lvs01 lvr01 toc011 toe01 clear output controller chapter 6 16-bit timer/event counter 109 user? manual u13029ej7v1ud when cr00n is used as a compare register the value set in cr00n is constantly compared with the 16-bit timer counter 0n (tm0n) count value, and an interrupt request (inttm00n) is generated if they match. it can also be used as the register that holds the interval time when tm0n is set to interval timer operation. when cr00n is used as a capture register it is possible to select the valid edge of the ti00n pin or the ti01n pin as the capture trigger. setting of the ti00n or ti01n valid edge is performed by means of prescaler mode register 0n (prm0n). if cr00n is specified as a capture register and the capture trigger is specified to be the valid edge of the ti00n pin, the situation is as shown in table 6-2. on the other hand, when the capture trigger is specified to be the valid edge of the ti01n pin, the situation is as shown in table 6-3. table 6-2. ti00n pin valid edge and cr00n, cr01n capture triggers es0n1 es0n0 ti00n pin valid edge cr00n capture trigger cr01 capture trigger 00 falling edge rising edge falling edge 01 rising edge falling edge rising edge 10 setting prohibited setting prohibited setting prohibited 11 both rising and falling edges no capture operation both rising and falling edges n = 0, 1 table 6-3. ti01n pin valid edge and cr00n capture trigger es1n1 es1n0 ti01n pin valid edge cr00n capture trigger 00 falling edge falling edge 01 rising edge rising edge 10 setting prohibited setting prohibited 11 both rising and falling edges both rising and falling edges n = 0, 1 cr00n is set by a 16-bit memory manipulation instruction. reset input makes the value of cr00n undefined. cautions 1. in the clear & start mode entered on a match between tm0n and cr00n, set cr00n to a value other than 0000h. however, in the free-running mode and the clear mode of the valid edge of ti00n, if cr00n is set to 0000h, an interrupt request (inttm00n) is generated after the overflow (ffffh). 2. if the value of cr00n after changing is smaller than the value of 16-bit timer counter 0n (tm0n), tm0n continues counting and overflows, then starts counting again from 0. also, if the value of cr00n after changing is less than the value before changing, it is necessary to restart the timer after cr00n changes. 3. when p54 (p56) is used as the valid edge of ti000 (ti001), it cannot be used as the timer output (to00 (to01)). also, if it is used as to00 (to01), it cannot be used as the valid edge of ti000 (ti001). remark n = 0, 1 chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 110 (3) 16-bit capture/compare register 010, 011 (cr010, cr011) cr010 and cr011 are 16-bit registers that have the functions of both a capture register and a compare register. whether to be used as a capture register or a compare register is set by bit 2 (crc0n2) of capture/compare control register 0n (crc0n). when cr01n is used as a compare register the value set in cr01n is constantly compared with the 16-bit timer counter 0n (tm0n) count value, and an interrupt request (inttm01n) is generated if they match. when cr01n is used as a capture register it is possible to select the valid edge of the ti00n pin as the capture trigger. the ti00n valid edge is set by means of prescaler mode register 0n (prm0n). cr01n is set by a 16-bit memory manipulation instruction. reset input makes the value of cr01n undefined. caution in the clear & start mode entered on a match between tm0n and cr00n, set cr01n to a value other than 0000h. however, in the free-running mode and the clear mode of the valid edge of ti00n, if cr01n is set to 0000h, an interrupt request (inttm01n) is generated after the overflow (ffffh). remark n = 0, 1 6.4 registers controlling 16-bit timer/event counter the following nine types of registers are used to control 16-bit timer/event counters 00 and 01. 16-bit timer mode control register 00, 01 (tmc00, tmc01) capture/compare control register 00, 01 (crc00, crc01) timer output control register 00, 01 (toc00, toc01) prescaler mode register 00, 01 (prm00, prm01) port mode register 5 (pm5) (1) 16-bit timer mode control register 00, 01 (tmc00, tmc01) these registers set the 16-bit timer operating mode, 16-bit timer counter 00, 01 (tm00, tm01) clear mode, and output timing, and detect an overflow. tmc00 and tmc01 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc00 and tmc01 to 00h. caution 16-bit timer counter 0n (tm0n) starts operating the instant that tmc0n2 and tmc0n3 (n = 0, 1) are set to a value other than 0 (operation stop mode). to stop operation, set tmc0n2 and tmc0n3 to 0. chapter 6 16-bit timer/event counter 111 user? manual u13029ej7v1ud figure 6-3. format of 16-bit timer mode control register 00 tmc003 tmc002 tmc001 operating mode to00 output timing selection interrupt request generation and clear mode selection 000 operation stop no change not generated 001 (tm00 cleared to 0) 010 free-running mode match between tm00 and cr000 or match between tm00 and cr010 011 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge 100 clear & start on ti000 valid 101 edge 110 clear & start on match match between tm00 and between tm00 and cr000 cr000 or match between tm00 and cr010 111 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge ovf00 16-bit timer counter 00 (tm00) overflow detection 0 overflow not detected 1 overflow detected cautions 1. write to a bit other than the ovf00 flag after timer operation stops. 2. set the valid edge of the ti000/to00/intp4/p54 pin with prescaler mode register 00 (prm00). 3. if clear & start mode entered on a match between tm00 and cr000 is selected, when the set value of cr000 is ffffh and the tm00 value changes from ffffh to 0000h, the ovf00 flag is set to 1. remarks to00: 16-bit timer/event counter 00 output pin ti000: 16-bit timer/event counter 00 input pin tm00: 16-bit timer counter 00 cr000: 16-bit capture/compare register 000 cr010: 16-bit capture/compare register 010 generated on match between tm00 and cr000, or match between tm00 and cr010 000 tmc002 tmc001 ovf00 tmc00 ff60h 00h r/w 54 symbol address after reset r/w tmc003 76 32 0 1 0 chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 112 figure 6-4. format of 16-bit timer mode control register 01 tmc013 tmc012 tmc011 operating mode to01 output timing selection interrupt request generation and clear mode selection 000 operation stop no change not generated 001 (tm01 cleared to 0) 010 free-running mode match between tm01 and cr001 or match between tm01 and cr011 011 match between tm01 and cr001, match between tm01 and cr011 or ti001 valid edge 100 clear & start on ti001 valid 101 edge 110 clear & start on match match between tm01 and between tm01 and cr001 cr001 or match between tm01 and cr011 111 match between tm01 and cr001, match between tm01 and cr011 or ti001 valid edge ovf01 16-bit timer counter 01 (tm01) overflow detection 0 overflow not detected 1 overflow detected cautions 1. write to a bit other than the ovf01 flag after timer operation stops. 2. set the valid edge of the ti001/to01/intp6/p56 pin with prescaler mode register 01 (prm01). 3. if clear & start mode entered on a match between tm01 and cr001 is selected, when the set value of cr001 is ffffh and the tm01 value changes from ffffh to 0000h, the ovf01 flag is set to 1. remarks to01: 16-bit timer/event counter 01 output pin ti001: 16-bit timer/event counter 01 input pin tm01: 16-bit timer counter 01 cr001: 16-bit capture/compare register 001 cr011: 16-bit capture/compare register 011 generated on match between tm01 and cr001, or match between tm01 and cr011 000 tmc012 tmc011 ovf01 tmc01 ff68h 00h r/w 54 symbol address after reset r/w tmc013 76 32 0 1 0 chapter 6 16-bit timer/event counter 113 user? manual u13029ej7v1ud (2) capture/compare control register 00, 01 (crc00, crc01) these registers control the operation of the 16-bit capture/compare registers (cr000, cr010, cr001, cr011). crc00 and crc01 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets crc00 and crc01 to 00h. figure 6-5. format of capture/compare control register 00 cautions 1. timer operation must be stopped before setting crc00. 2. when clear & start mode entered on a match between tm00 and cr000 is selected with 16- bit timer mode control register 00 (tmc00), cr000 should not be specified as a capture register. 3. if both the rising and falling edges are selected as the valid edges of ti000, capture is not performed. 4. in order to ensure the capture operation, a pulse longer than two clocks of the count clock specified by prescaler mode register 00 (prm00) is required for a capture trigger. 0 000 crc002 crc001 crc000 crc00 crc002 cr010 operating mode selection 0 1 operates as compare register operates as capture register crc001 cr000 capture trigger selection 0 1 captures on valid edge of ti010 captures on inverted phase of valid edge of ti000 crc000 cr000 operating mode selection 0 1 operates as compare register operates as capture register ff62h 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 114 0 000 crc012 crc011 crc010 crc01 crc012 cr011 operating mode selection 0 1 operates as compare register operates as capture register crc011 cr001 capture trigger selection 0 1 captures on valid edge of ti011 captures on inverted phase of valid edge of ti001 crc010 cr001 operating mode selection 0 1 operates as compare register operates as capture register ff6ah 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 figure 6-6. format of capture/compare control register 01 cautions 1. timer operation must be stopped before setting crc01. 2. when clear & start mode on a match between tm01 and cr001 is selected with 16-bit timer mode control register 01 (tmc01), cr001 should not be specified as a capture register. 3. if both the rising and falling edges are selected as the valid edges of ti001, capture is not performed. 4. in order to ensure the capture operation, a pulse longer than two clocks of the count clock specified by prescaler mode register 01 (prm01) is required for a capture trigger. chapter 6 16-bit timer/event counter 115 user? manual u13029ej7v1ud (3) timer output control register 00, 01 (toc00, toc01) these registers control the operation of the 16-bit timer/event counter 00, 01 output control circuit, including r- s type flip-flop (lv0) setting/resetting, output inversion enabling/disabling, and 16-bit timer/event counter 00, 01 timer output enabling/disabling. toc00 and toc01 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets toc00 and toc01 to 00h. figure 6-7. format of timer output control register 00 cautions 1. timer operation must be stopped before setting toc00. 2. be sure to set bits 5 to 7 of toc00 to 0. remark if lvs00 and lvr00 are read after data is set, they will be 0. 000 toc004 lvr00 toc001 toe00 toc00 toc004 timer output f/f control by match of cr010 and tm00 0 1 inversion operation disabled inversion operation enabled toc001 timer output f/f control by match of cr000 and tm00 0 1 inversion operation disabled inversion operation enabled toe00 16-bit timer/event counter 00 timer output control 0 1 output disabled (output set to level 0) output enabled lvs00 lvr00 16-bit timer/event counter 00 timer output f/f status setting 0 0 0 1 no change timer output f/f reset (0) 1 1 0 1 timer output f/f set (1) setting prohibited ff63h 00h r/w 54 symbol address after reset r/w lvs00 76 32 0 1 chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 116 figure 6-8. format of timer output control register 01 cautions 1. timer operation must be stopped before setting toc01. 2. be sure to set bits 5 to 7 of toc01 to 0. remark if lvs01 and lvr01 are read after data is set, they will be 0. 000 toc014 lvr01 toc011 toe01 toc01 toc014 timer output f/f control by match of cr011 and tm01 0 1 inversion operation disabled inversion operation enabled toc011 timer output f/f control by match of cr001 and tm01 0 1 inversion operation disabled inversion operation enabled toe01 16-bit timer/event counter 01 timer output control 0 1 output disabled (output set to level 0) output enabled lvs01 lvr01 16-bit timer/event counter 01 timer output f/f status setting 0 0 0 1 no change timer output f/f reset (0) 1 1 0 1 timer output f/f set (1) setting prohibited ff6bh 00h r/w 54 symbol address after reset r/w lvs01 76 32 0 1 chapter 6 16-bit timer/event counter 117 user? manual u13029ej7v1ud (4) prescaler mode register 00, 01 (prm00, prm01) this register is used to set the 16-bit timer counter 00, 01 (tm00, tm01) count clock and ti000, ti001 input valid edges. prm00 and prm01 are set by an 8-bit memory manipulation instruction. reset input sets prm00 and prm01 to 00h. figure 6-9. format of prescaler mode register 00 notes 1. expanded-specification products only 2. the external clock requires a pulse longer than two internal clocks (f x /2 4 ). cautions 1. if the valid edge of ti000 is set for the count clock, do not set it for the clear & start mode or the capture trigger. also, the p54/ti000/to00/intp4 pin cannot be used as a timer output (to00). 2. prm00 should be set only after timer operation has been stopped. 3. if the ti000 pin or ti010 pin is high level immediately after system reset, and the rising edge or both edges are specified as the valid edge of ti000 pin or ti010 pin thus enabling operation of 16-bit timer counter 00 (tm00), the rising edge will be detected immediately. care is therefore needed if the ti000 pin or ti010 pin is pulled up. when operation is enabled again after being stopped, the rising edge cannot be detected. remarks 1. f x : system clock oscillation frequency 2. ti000, ti010: input pins of 16-bit timer/event counter 00 es101 es100 es001 es000 0 prm001 prm000 prm00 es101 es100 ti010 valid edge selection 0 0 0 1 falling edge rising edge 1 1 0 1 setting prohibited both falling and rising edges es001 es000 ti000 valid edge selection 0 0 0 1 falling edge rising edge 1 1 0 1 setting prohibited both falling and rising edges prm001 prm000 count clock selection 0 0 0 1 fx fx/2 2 1 1 0 1 fx/2 5 ti000 valid edge note 2 ff61h 00h r/w 54 symbol address after reset r/w 0 76 3 2 0 1 12 mhz 3 mhz 375 khz 8.38 mhz 2.09 mhz 262 khz at f x = 12 mhz note 1 at f x = 8.38 mhz chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 118 figure 6-10. format of prescaler mode register 01 notes 1. expanded-specification products only 2. the external clock requires a pulse longer than two internal clocks (f x /2 4 ). cautions 1. if the valid edge of ti001 is set for the count clock, do not set it for the clear and start mode or the capture trigger. also, the p56/ti001/to01/intp6 pin cannot be used as a timer output (to01). 2. prm01 should be set only after timer operation has been stopped. 3. if the ti001 pin or ti011 pin is high level immediately after system reset, and the rising edge or both edges are specified as the valid edge of the ti001 pin or ti011 pin thus enabling operation of 16-bit timer counter 01 (tm01), the rising edge will be detected immediately. care is therefore needed if the ti001 pin or ti011 pin is pulled up. when operation is enabled again after being stopped, the rising edge cannot be detected. remarks 1. f x : system clock oscillation frequency 2. ti001, ti011: input pins of 16-bit timer/event counter 01 es111 es110 es011 es010 0 prm011 prm010 prm01 es111 es110 ti011 valid edge selection 0 0 0 1 falling edge rising edge 1 1 0 1 setting prohibited both falling and rising edges es011 es010 ti001 valid edge selection 0 0 0 1 falling edge rising edge 1 1 0 1 setting prohibited both falling and rising edges prm011 prm010 count clock selection 0 0 0 1 fx fx/2 2 1 1 0 1 fx/2 5 ti001 valid edge note 2 ff61h 00h r/w 54 symbol address after reset r/w 0 76 3 2 0 1 12 mhz 3 mhz 375 khz 8.38 mhz 2.09 mhz 262 khz at f x = 12 mhz note 1 at f x = 8.38 mhz chapter 6 16-bit timer/event counter 119 user? manual u13029ej7v1ud (5) port mode register 5 (pm5) this register sets port 5 to input/output in 1-bit units. when using the p54/to00/ti000/intp4 pin or p56/to01/ti001/intp6 pin for timer output, set pm54 or pm56 and the output latch of p54 or p56 to 0. pm5 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm5 to ffh. figure 6-11. format of port mode register 5 pm57 pm56 pm55 pm54 pm52 pm51 pm50 pm5 pm5n p5n pin input/output mode selection (n = 0 to 7) 0 1 output mode (output buffer on) input mode (output buffer off) ff25h ffh r/w 54 symbol address after reset r/w pm53 76 32 0 1 chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 120 6.5 operation of 16-bit timer/event counter 6.5.1 interval timer operation setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 6-12 allows operation as an interval timer. interrupt requests are generated repeatedly using the count value preset in 16-bit capture/compare register 00n (cr00n) as the interval. when the count value of 16-bit timer counter 0n (tm0n) matches the value set to cr00n, counting continues with the tm0n value cleared to 0 and the interrupt request signal (inttm00n) is generated. the count clock of tm0n can be selected with bits 0 and 1 (prm0n0, prm0n1) of prescaler mode register 0n (prm0n). see 6.6 notes on 16-bit timer/event counter (3) operation after compare register change during timer count operation about the operation when the compare register value is changed during timer count operation. remark n = 0, 1 figure 6-12. control register settings for interval timer operation (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see figures 6-3 to 6-6. 2. n = 0, 1 0000 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. 00000 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n as compare register chapter 6 16-bit timer/event counter 121 user? manual u13029ej7v1ud figure 6-13. interval timer configuration diagram remark n = 0, 1 figure 6-14. timing of interval timer operation remarks 1. interval time = (n + 1) t: n = 0001h to ffffh 2. n = 0, 1 count clock t tm0n count value cr00n inttm00n to0n 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n count start clear clear interrupt request acknowledged interrupt request acknowledged interval time interval time interval time 16-bit capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) ovf0n clear circuit inttm00n selector f x f x /2 2 f x /2 4 f x /2 5 ti00n noise eliminator chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 122 6.5.2 ppg output operation setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 6-15 allows operation as ppg (programmable pulse generator) output. in the ppg output operation, square waves are output from the to0n pin with the pulse width and the cycle that correspond to the count values preset in 16-bit capture/compare register 01n (cr01n) and in 16-bit capture/compare register 00n (cr00n). remark n = 0, 1 figure 6-15. control register settings for ppg output operation (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 1 tmc0n2 1 tmc0n1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. 00000 crc0n2 0 crc0n1 crc0n0 0 crc0n cr00n as compare register cr01n as compare register (b) capture/compare control register 0n (crc0n) (c) timer output control register 0n (toc0n) cautions 1. values in the following range should be set in cr00n and cr01n: 0000h < cr01n < cr00n ffffh 2. the cycle of the pulse generated by ppg output becomes (cr00n setting + 1), and the duty becomes (cr01n setting + 1)/(cr00n setting + 1). remark : don? care n = 0, 1 000 toc0n4 1 lvs0n 0/1 lvr0n 0/1 toc0n1 1 toe0n 1 toc0n enables to0n output inverts output on match between tm0n and cr00n specifies initial value of to0n output f/f inverts output on match between tm0n and cr01n chapter 6 16-bit timer/event counter 123 user? manual u13029ej7v1ud figure 6-16. configuration diagram of ppg output remark n = 0, 1 figure 6-17. ppg output operation timing remarks 1. 0000h < m < n ffffh 2. n = 0, 1 16-bit timer capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) clear circuit f x f x /2 2 f x /2 5 16-bit timer capture/compare register 01n (cr01n) to0n selector output controller t 0000h 0000h 0001h 0001h m ? 1 count clock tm0n count value to0n pulse width: (m + 1) one cycle (n + 1) n value loaded to cr00n value loaded to cr01n m m n ? 1 n clear count start chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 124 6.5.3 pulse width measurement operation it is possible to measure the pulse width of the signals input to the ti00n and ti01n pins using 16-bit timer counter 0n (tm0n). there are two measurement methods: measuring with tm0n used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti00n pin. (1) pulse width measurement with free-running counter and one capture register when 16-bit timer counter 0n (tm0n) is operated in free-running mode (see register settings in figure 6-18 ), and the edge specified by prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit capture/compare register 01n (cr01n) and an external interrupt request signal (inttm01n) is set. the valid edge of the ti00n pin is specified by bits 4 and 5 (es0n0, es0n1) of prm0n, and the rising edge, falling edge or both edges can be selected. when sampling is performed at the count clock cycle selected by prm0n and the valid level of the ti00n pin is detected twice, the first capture operation is performed, resulting in the elimination of short pulse width noise. remark n = 0, 1 figure 6-18. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register 0n (tmc0n) 0000 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode 00000 crc0n2 1 crc0n1 0/1 crc0n0 0 crc0n cr00n as compare register cr01n as capture register (b) capture/compare control register 0n (crc0n) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figures 6-3 to 6-6 for details. 2. n = 0, 1 chapter 6 16-bit timer/event counter 125 user? manual u13029ej7v1ud figure 6-19. configuration diagram for pulse width measurement with free-running counter remark n = 0, 1 figure 6-20. timing of pulse width measurement operation with free-running counter and one capture register (with both edges specified) remark n = 0, 1 f x f x /2 2 f x /2 5 selector ti00n 16-bit timer counter 0n (tm0n) ovf0n 16-bit capture/compare register 01n (cr01n) internal bus inttm01n count clock tm0n count value ti00n pin input value loaded to cr01n inttm01n ovf0n (d1 ?d0) t (10000h ?d1 + d2) t (d3 ?d2) t 0000h 0000h ffffh 0001h d0 t d0+1 d1 d0 d1 d2 d3 d2 d3 d1+1 chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 126 (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 0n (tm0n) is operated in free-running mode (see register settings in figure 6-21 ), it is possible to simultaneously measure the pulse widths of the two signals input to the ti00n and the ti01n pins. when the edge specified by bits 4 and 5 (es0n0, es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit capture/compare register 01n (cr01n) and an external interrupt request signal (inttm01n) is set. also, when the edge specified by bits 6 and 7 (es1n0, es1n1) of prm0n is input to the ti01n pin, the value of tm0n is taken into 16-bit capture/compare register 00n (cr00n) and an external interrupt request signal (inttm00n) is set. the valid edges of the ti00n and ti01n pins are specified by bits 4 and 5 (es0n0, es0n1), and bits 6 and 7 (es1n0, es1n1) of prm0n, respectively. it is possible to select the rising edge, falling edge or both edges as the valid edge. when sampling is performed at the count clock cycle selected by prm0n and the valid level of the ti00n or ti01 pin is detected twice, the first capture operation is performed, resulting in the elimination of short pulse width noise. remark n = 0, 1 figure 6-21. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register 0n (tmc0n) 00000 crc0n2 1 crc0n1 0 crc0n0 1 crc0n cr00n as capture register captures valid edge of ti01n pin to cr00n cr01n as capture register 0000 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare control register 0n (crc0n) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figures 6-3 and 6-4 for details. 2. n = 0, 1 chapter 6 16-bit timer/event counter 127 user? manual u13029ej7v1ud capture operation (free-running mode) the capture register operation of when the capture trigger is input is shown. figure 6-22. cr01n capture operation with rising edge specified remark n = 0, 1 figure 6-23. timing of pulse width measurement operation with free-running counter (with both edges specified) remark n = 0, 1 count clock tm0n ti00n rising edge detection cr01n inttm01n n ?3 n ?2 n ?1 n n + 1 n count clock tm0n count value ti00n pin input value loaded to cr01n inttm01n ti01n pin input value loaded to cr00n inttm00n ovf0n (d1 ?d0) t (10000h ?d1 + d2) t (10000h ?d1 + (2 + 1)) t (d3 ?d2) t t 0000h 0001h ffffh 0000h d0 d0 d0+1 d1 d1+1 d2 d2+1 d2+2 d3 d1 d1 d2 +1 d2 chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 128 (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer counter 0n (tm0n) is operated in free-running mode (see register settings in figure 6-24 ), it is possible to measure the pulse width of the signal input to the ti00n pin. when the edge specified by bits 4 and 5 (es0n0, es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit capture/compare register 01n (cr01n) and an external interrupt request signal (inttm01n) is set. also, when the inverse edge to that of the capture operation to cr01n is input, the value of tm0n is taken into 16-bit capture/compare register 00n (cr00n). the valid edge of the ti00n pin is specified by bits 4 and 5 (es0n0, es0n1) of prm0n, and it is possible to select the rising edge or falling edge. when sampling is performed at the count clock cycle selected by prm0n and the valid level of the ti00n pin is detected twice, the first capture operation is performed, resulting in the elimination of short pulse width noise. caution if the valid edge of the ti00n pin is specified to be both the rising and falling edges, capture/ compare register 00n (cr00n) cannot perform the capture operation. remark n = 0, 1 figure 6-24. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register 0n (tmc0n) 00000 crc0n2 1 crc0n1 1 crc0n0 1 crc0n cr00n as capture register captures to cr00n at edge reverse to valid edge of ti00n cr01n as capture register 0000 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare control register 0n (crc0n) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figures 6-3 and 6-4 for details. 2. n = 0, 1 chapter 6 16-bit timer/event counter 129 user? manual u13029ej7v1ud figure 6-25. timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) remark n = 0, 1 (4) pulse width measurement by means of restart when input of a valid edge to the ti00n pin is detected, the count value of 16-bit timer counter 0n (tm0n) is taken into 16-bit capture/compare register 01n (cr01n), and then the pulse width of the signal input to the ti00n pin is measured by clearing tm0n and restarting the count (see register settings in figure 6-26 ). the valid edge of the ti00n pin is specified by bits 4 and 5 (es0n0, es0n1) of prescaler mode register 0n (prm0n), and it is possible to select either the rising edge or falling edge. when sampling is performed at the count clock cycle selected by prm0n and the valid level of the ti00n pin is detected twice, the first capture operation is performed, resulting in the elimination of short pulse width noise. caution if the valid edge of the ti00n pin is specified to be both the rising and falling edges, capture/ compare register 00n (cr00n) cannot perform the capture operation. remark n = 0, 1 t count clock tm0n count value ti00n pin input value loaded to cr01n value loaded to cr00n inttm01n ovf0n 0000h 0001h d0 d0+1 d1 d1+1 d2 d2+1 ffffh 0000h d3 d0 d2 d3 d1 (d1 ?d0) t (10000h ?d1 + d2) t (d3 ?d2) t chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 130 figure 6-26. control register settings for pulse width measurement by means of restart (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see figures 6-3 and 6-4 for details. 2. n = 0, 1 figure 6-27. timing of pulse width measurement operation by means of restart (with rising edge specified) remark n = 0, 1 0000 tmc0n3 1 tmc0n2 0 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts at valid edge of ti00n pin. 00000 crc0n2 1 crc0n1 1 crc0n0 1 crc0n cr00n as capture register cr01n as capture register captures to cr00n at edge reverse to valid edge of ti00n. t count clock tm0n count value ti00n pin input value loaded to cr01n value loaded to cr00n inttm01n 0000h 0001h d0 d0 d2 d1 d1 0000h 0001h d2 0000h 0001h d1 t d2 t chapter 6 16-bit timer/event counter 131 user? manual u13029ej7v1ud 6.5.4 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti00n pin by 16-bit timer counter 0n (tm0n). tm0n is incremented each time the valid edge specified by prescaler mode register 0n (prm0n) is input. when the tm0n count value matches the 16-bit capture/compare register 00n (cr00n) value, tm0n is cleared to 0 and an interrupt request signal (inttm00n) is generated. a value other than 0000h should be set for cr00n (a 1-pulse count operation is not possible). specify the valid edge of the ti00n pin using bits 4 and 5 (es0n0, es0n1) of prm0n. it is possible to select the rising edge, falling edge or both edges. when sampling is performed at the internal clock (f x /2 4 ) and the valid level of the ti00n pin is detected twice, the first capture operation is performed, resulting in the elimination of short pulse width noise. caution when the 16-bit timer/event counter is being used as an external event counter, the p54/ti000/ to00/intp4 pin (p56/ti001/to01/intp6 pin) cannot be used for timer output (to00 (to01)). remark n = 0, 1 figure 6-28. control register settings in external event counter mode (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see figures 6-3 to 6-6 for details. 2. n = 0, 1 0000 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. 00000 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n as compare register chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 132 figure 6-29. external event counter configuration diagram remark n = 0, 1 figure 6-30. external event counter operation timings (with rising edge specified) caution when reading the external event counter count value, tm0n (n = 0, 1) should be read. remark n = 0, 1 6.5.5 square-wave output operation this is an operation whereby a square wave with any selected frequency is output using the count value preset to 16-bit capture/compare register 00n (cr00n) as the interval. the to0n pin output status is inverted at the intervals of the count value preset to cr00n by setting bit 0 (toe0n) and bit 1 (toc0n1) of timer output control register 0n (toc0n) to 1. this enables a square wave with any selected frequency to be output. remark n = 0, 1 ti00n pin input tm0n count value cr00n inttm00n 0000h 0001h 0002h 0003h 0004h 0005h n ?1 n 0000h 0001h 0002h 0003h n 16-bit capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) 16-bit capture/compare register 01n (cr01n) internal bus match clear ovf0n inttm00n f x /2 2 f x /2 5 f x noise eliminator noise eliminator f x /2 4 valid edge of ti00n selector chapter 6 16-bit timer/event counter 133 user? manual u13029ej7v1ud figure 6-31. control register settings in square-wave output mode (a) 16-bit timer mode control register 0n (tmc0n) (b) capture/compare control register 0n (crc0n) (c) timer output control register 0n (toc0n) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see figures 6-3 to 6-8 for details. 2. n = 0, 1 figure 6-32. square-wave output operation timing remark n = 0, 1 0000 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. 00000 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n as compare register 000 toc0n4 0 lvs0n 0/1 lvr0n 0/1 toc0n1 1 toe0n 1 toc0n enables to0n output. inverts output on match between tm0n and cr00n. specifies initial value of to0n output f/f. does not invert output on match between tm0n and cr01n. count clock tm0n count value cr00n inttm00n to0n pin output 0000h 0001h 0002h n ?1 n 0000h 0001h 0002h n ?1 n 0000h n chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 134 6.6 notes on 16-bit timer/event counter (1) timer start errors an error of a maximum of one clock may occur during the time required for a match signal to be generated after timer start. this is because 16-bit timer counter 0n (tm0n: n = 0, 1) is started asynchronously to the count clock. figure 6-33. 16-bit timer counter start timing remark n = 0, 1 (2) 16-bit compare register setting (clear & start mode entered on a match between tm0n and cr00n) set 16-bit capture/compare registers 00n, 01n (cr00n, cr01n: n = 0, 1) to other than 0000h. this means a 1- pulse count operation cannot be performed when they are used as event counters. (3) operation after compare register change during timer count operation if the value after the change of 16-bit capture/compare register 00n (cr00n: n = 0, 1) is smaller than that of 16- bit timer counter 0n (tm0n: n = 0, 1), tm0n continues counting, overflows and then restarts counting from 0. thus, if the value (m) after the cr00n change is smaller than that (n) before the change, it is necessary to reset the timer to restart after cr00n is changed. figure 6-34. timing after change of compare register during timer count operation remark n > x > m n = 0, 1 tm0n count value 0000h 0001h 0002h 0004h count clock timer start 0003h cr00n nm count clock tm0n count value x ?1 x ffffh 0000h 0001h 0002h chapter 6 16-bit timer/event counter 135 user? manual u13029ej7v1ud (4) capture register data retention timing if the valid edge of the ti00n pin is input during 16-bit capture/compare register 01n (cr01n) read, cr01n performs a capture operation, but the capture value at this time is not guaranteed. however, the interrupt request signal (tmif01n) is set upon detection of the valid edge. remark n = 0, 1 figure 6-35. capture register data retention timing remark n = 0, 1 (5) valid edge setting set the valid edge of the ti00n pin after setting bits 2 and 3 (tmc0n2 and tmc0n3) of 16-bit timer mode control register 0n (tmc0n) to 0, and stopping timer operation. the valid edge is set with bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). remark n = 0, 1 count clock tm0n count value edge input interrupt request flag capture read signal cr01n interrupt value nn + 1 n + 2 m m + 1 m + 2 xn + 1 capture operation, but not guaranteed capture operation chapter 6 16-bit timer/event counter user? manual u13029ej7v1ud 136 (6) operation of ovf0n flag <1> the ovf0n flag (bit 6 of 16-bit timer mode control register 0n (tmc0n)) is set to 1 the next time. one of clear & start mode entered on match between tm0n and cr00n, clear & start mode entered at the valid edge of ti00n, and free-running mode is selected. cr00n is set to ffffh. when tm0n is counted up from ffffh to 0000h. remark n = 0, 1 figure 6-36. operation timing of ovf0n flag remark n = 0, 1 <2> after tm0n overflows, it is reset and the clear instruction becomes invalid even though the ovf0n flag is cleared before the next count clock (before tm0n becomes 0001h). remark n = 0, 1 (7) conflicting operations <1> conflicting operations between the read time of 16-bit capture/compare register 00n, 01n (cr00n, cr01n) and capture trigger input (cr00n and cr01n used as capture register) capture trigger input has priority. the data read from cr00n and cr01n is undefined. <2> match timing of conflicting operations between the write period of 16-bit capture/compare register 00n, 01n (cr00n, cr01n) and 16-bit timer counter 0n (tm0n) (cr00n and cr01n used as compare register) match judgement is not performed normally. do not write any data to cr00n and cr01n near the match timing. remark n = 0, 1 count clock cr00n tm0n ovf0n inttm00n ffffh fffeh ffffh 0000h 0001h chapter 6 16-bit timer/event counter 137 user? manual u13029ej7v1ud (8) timer operation <1> even if 16-bit timer counter 0n (tm0n) is read, the value is not captured in 16-bit capture/compare register 01n (cr01n). <2> regardless of the operation mode of the cpu, if the timer is stopped, the noise of the external interrupt request input is not removed. remark n = 0, 1 (9) capture operation <1> when the valid edge of ti00n (n = 0, 1) is specified for the count clock, the capture register that specified ti00n as the trigger cannot perform the capture operation normally. <2> a capture operation is not performed when both the rising and falling edges are specified for the ti00n valid edge. <3> in order to ensure the capture operation, a pulse longer than two clocks of the count clock specified by prescaler mode register 0n (prm0n) is required for a capture trigger. <4> capture operations start at the falling edge of the count clock. however, interrupt request input (inttm00n) starts at the rising edge of the count clock. remark n = 0, 1 (10) compare operation <1> if values are written to 16-bit capture/compare registers 00n and 01n (cr00n, cr01n) at the timing when the set values of cr00n and cr01n and the count value of 16-bit timer counter 0n (tm0n) match generating inttm00n and inttm01n, inttm00n and inttm01n may not be generated. therefore, do not write values to cr00n and cr01n repeatedly even if the values are the same. <2> cr00n and cr01n set in the compare mode cannot perform a capture operation even if the capture trigger is input. remark n = 0, 1 (11) edge detection <1> when the ti00n pin or the ti01n pin is high level immediately after system reset, and if the rising edge or both edges are specified as the valid edge of the ti00n pin or the ti01n pin, then the rising edge is detected immediately after operation of 16-bit timer counter 0n (tm0n) is enabled. be careful when the ti00n pin or the ti01n pin is pulled up. when operation is enabled again after once being stopped, the rising edge cannot be detected. <2> a different sampling clock for noise elimination is used when the ti00n pin valid edge is used for the count clock and when it is used for capture trigger. in the former case, a count clock of f x /2 4 is used, and in the latter case the count clock specified by prescaler mode register 0n (prm0n) is used for sampling. a capture operation is only performed when sampling is performed at the above described sampling clock and when a valid level is detected twice, thus eliminating noise with a short-pulse width. remark n = 0, 1 user? manual u13029ej7v1ud 138 chapter 7 8-bit timer/event counter 7.1 outline of 8-bit timer/event counter an 8-bit timer/event counter can be used as an interval timer, external event counter, to output a square wave with any selected frequency, and for pwm output. two 8-bit timer/event counters can be used as one 16-bit timer/event counter. 7.2 function of 8-bit timer/event counter the 8-bit timer/event counters (50, 51, and 52) have the following two modes. mode in which an 8-bit timer/event counter is used alone (single mode) mode in which two or more 8-bit timer/event counters are connected in cascade (16-bit resolution: cascade mode) these two modes are explained below. (1) mode in which an 8-bit timer/event counter is used alone (single mode) in this mode, the 8-bit timer/event counter can be used for the following functions. interval timer external event counter square-wave output pwm output (2) mode in which tm50 and tm51, or tm51 and tm52 are connected in cascade (16-bit resolution: cascade mode) by connecting 8-bit timer/event counters in cascade, they can be used as a 16-bit timer/event counter. in the cascade mode, the 8-bit timer/event counters can be used for the following functions. 16-bit resolution interval timer 16-bit resolution external event counter 16-bit resolution square-wave output chapter 7 8-bit timer/event counter 139 user? manual u13029ej7v1ud 7.3 configuration of 8-bit timer/event counter an 8-bit timer/event counter includes the following hardware. table 7-1. configuration of 8-bit timer/event counter item timer register register timer output control registers configuration 8-bit timer counter 5n (tm5n) 8-bit compare register 5n (cr5n) to5n 8-bit timer mode control register 5n (tmc5n) timer clock select register 5n (tcl5n) port mode register 2 (pm2) note note refer to figure 4-4 block diagram of p20 to p26 . remark n = 0 to 2 figure 7-1. block diagram of 8-bit timer/event counter 50 internal bus internal bus ti50/to50/p24 f x /2 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 11 selector 8-bit compare register 50 (cr50) match 8-bit timer counter 50 (tm50) 3 selector mask circuit clear ovf tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) 8-bit timer mode control register 50 (tmc50) tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 s r inv s q r selector inttm50 selector to50/ti50/p24 level inversion chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 140 internal bus internal bus ti51/to51/p25 f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 selector 8-bit compare register 51 (cr51) match 8-bit timer counter 51 (tm51) 3 selector mask circuit clear ovf tcl512 tcl511 tcl510 timer clock select register 51 (tcl51) 8-bit timer mode control register 51 (tmc51) tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 s r inv s q r selector inttm51 selector to51/ti51/p25 level inversion figure 7-2. block diagram of 8-bit timer/event counter 51 figure 7-3. block diagram of 8-bit timer/event counter 52 internal bus internal bus ti52/to52/p26 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 selector 8-bit compare register 52 (cr52) match 8-bit timer counter 52 (tm52) 3 selector mask circuit clear ovf tcl522 tcl521 tcl520 timer clock select register 52 (tcl52) 8-bit timer mode control register 52 (tmc52) tce52 tmc526 tmc524 lvs52 lvr52 tmc521 toe52 s r inv s q r selector inttm52 selector to52/ti52/p26 level inversion chapter 7 8-bit timer/event counter 141 user? manual u13029ej7v1ud (1) 8-bit timer counters 50, 51, and 52 (tm50, tm51, and tm52) tm50, tm51, and tm52 are 8-bit read-only registers that count count pulses. these counters are incremented in synchronization with the rising edge of the count clock. tm50 and tm51, or tm51 and tm52 can be connected in cascade and used as a 16-bit timer. when tm50 and tm51 are connected in cascade and used as a 16-bit timer, the values of these timer counters can be read using a 16-bit manipulation instruction. tm50 and tm51 are connected with an internal 8-bit bus, and are read one at a time. this means that the value of tm50, for example, may change while that of tm51 is read. therefore, read tm50 and tm51 two times to compare their first and second values for the sake of accuracy. when tm51 and tm52 are connected in cascade and used as a 16-bit timer, they cannot be read using a 16-bit manipulation instruction. when reading tm51 and tm52, read them separately using an 8-bit manipulation instruction. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is cleared to 00h in the following cases. <1> reset input <2> clearing tce5n <3> match between tm5n and cr5n in clear & start mode caution in a cascade connection, the 16-bit timer is cleared to 00h regardless of whether tce51 of tm51 or tce52 of tm52 is cleared. remark n = 0 to 2 (2) 8-bit compare registers 50, 51, and 52 (cr50, cr51, and cr52) the value set to cr5n is always compared with the count value of 8-bit timer counter 5n (tm5n). when the value of the compare register matches the value of the timer counter, an interrupt request (inttm5n) is generated (in a mode other than the pwm mode). the value of cr5n can be set in the range of 00h to ffh and can be rewritten during counting. if tm50 and tm51 are connected in cascade and used as a 16-bit timer, cr50 and cr51 operate as a 16- bit compare register. therefore, the count value and register value are compared in 16-bit units, and if the two values match, an interrupt request (inttm50) is generated. at this time, the inttm51 interrupt request is also generated. when connecting tm50 and tm51 in cascade, therefore, mask the inttm51 interrupt request. the same applies when tm51 and tm52 are connected in cascade. if the value of the 16-bit timer matches that of the 16-bit compare register, the inttm51 interrupt request is generated (so mask the inttm52 interrupt request). cr50, cr51, and cr52 are set by an 8-bit memory manipulation instruction. when cr50 and cr51 are connected in cascade, these registers function as the cr5 register and can be accessed in 16 bits. reset input makes these registers undefined. caution when changing the setting value of 8-bit compare register 5n (cr5n) in cascade mode, stop each timer operation of 8-bit timer counter 5n (tm5n) connected in cascade. remark n = 0 to 2 chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 142 7.4 registers controlling 8-bit timer/event counter the following seven registers control 8-bit timer/event counters 50, 51, and 52. 8-bit timer mode control registers 50, 51, and 52 (tmc50, tmc51, and tmc52) timer clock select registers 50, 51, and 52 (tcl50, tcl51, and tcl52) port mode register 2 (pm2) (1) 8-bit timer mode control registers 50, 51, and 52 (tmc50, tmc51, and tmc52) tmc50, tmc51, and tmc52 perform the following six operations. <1> control of count operation of 8-bit timer counters 50, 51, and 52 (tm50, tm51, and tm52) <2> selection of operation mode of 8-bit timer counters 50, 51, and 52 (tm50, tm51, and tm52) <3> selection of single mode or cascade mode <4> setting of status of timer output f/f (flip-flop) <5> control of timer f/f or selection of active level in pwm (free-running) mode <6> control of timer output tmc50, tmc51, and tmc52 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. figures 7-4 to 7-6 show the formats of tmc50, tmc51, and tmc52. chapter 7 8-bit timer/event counter 143 user? manual u13029ej7v1ud figure 7-4. format of 8-bit timer mode control register 50 caution be sure to set (1) the interrupt mask flag (tmmk50) before clearing (0) tce50 to avoid generating an interrupt when tce50 is cleared. the procedure to clear (0) tce50 is as follows. tmmk50 = 1 ; mask set tce50 = 0 ; timer clear tmif50 = 0 ; interrupt request flag clear tmmk50 = 0 ; mask clear tce50 = 1 ; timer start remarks 1. the pwm output is at the inactive level in the pwm mode because tce50 = 0. 2. if lvs50 and lvr50 are read immediately after data has been set, these bits are 0. tce50 tmc506 0 lvr50 tmc501 toe50 tmc50 tm50 count operation control 0 1 disables count operation after clearing counter to 0 (disables prescaler). starts counting. tmc506 tm50 operating mode selection 0 1 clears and starts on match between tm50 and cr50. pwm (free-running) mode lvs50 timer output f/f status setting of 8-bit timer/event counter 50 0 0 not affected resets timer output f/f (to 0). tmc501 other than pwm mode (tmc506 = 0) 0 1 disables inverted operation. enables inverted operation. toe50 timer output control of 8-bit timer/event counter 50 0 1 disables output (port mode). enables output. ff70h 00h r/w 54 symbol address after reset r/w lvs50 76 32 0 1 tce50 0 lvr50 0 1 1 sets timer output f/f (to 1). 0 1 setting prohibited 1 pwm mode (tmc506 = 1) timer f/f control active level selection high active low active chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 144 figure 7-5. format of 8-bit timer mode control register 51 caution be sure to set (1) the interrupt mask flag tmmk51 before clearing (0) tce51 to avoid generating an interrupt when tce51 is cleared. the procedure to clear (0) tce51 is as follows. tmmk51 = 1 ; mask set tce51 = 0 ; timer clear tmif51= 0 ; interrupt request flag clear tmmk51 = 0 ; mask clear tce51 = 1 ; timer start remarks 1. pwm output is at the inactive level in the pwm mode because tce51 = 0. 2. if lvs51 and lvr51 are read immediately after data has been set, these bits are 0. tce51 tmc516 0 lvr51 tmc511 toe51 tmc51 tm51 count operation control 0 1 disables count operation after clearing counter to 0 (disables prescaler). starts counting. tmc516 tm51 operating mode selection 0 1 clears and starts on match between tm51 and cr51. pwm (free-running) mode tmc514 single mode/cascade mode selection 0 1 single mode cascade mode (connected to tm50) lvs51 timer output f/f status setting of 8-bit timer/event counter 51 0 0 not affected resets timer output f/f (to 0). tmc511 other than pwm mode (tmc516 = 0) 0 1 disables inverted operation. enables inverted operation. toe51 timer output control of 8-bit timer/event counter 51 0 1 disables output (port mode). enables output. ff74h 00h r/w 54 symbol address after reset r/w lvs51 76 32 0 1 tce51 tmc514 lvr51 0 1 1 sets timer output f/f (to 1). 0 1 setting prohibited 1 pwm mode (tmc516 = 1) timer f/f control active level selection high active low active chapter 7 8-bit timer/event counter 145 user? manual u13029ej7v1ud figure 7-6. format of 8-bit timer mode control register 52 caution be sure to set (1) the interrupt mask flag (tmmk52) before clearing (0) tce52 to avoid generating an interrupt when tce52 is cleared. the procedure to clear (0) tce52 is as follows. tmmk52 = 1 ; mask set tce52 = 0 ; timer clear tmif52 = 0 ; interrupt request flag clear tmmk52 = 0 ; mask clear tce52 = 1 ; timer start remarks 1. pwm output is at the inactive level in the pwm mode because tce52 = 0. 2. if lvs52 and lvr52 are read immediately after data has been set, these bits are 0. tce52 tmc526 0 lvr52 tmc521 toe52 tmc52 tm52 count operation control 0 1 disables count operation after clearing counter to 0 (disables prescaler). starts counting. tmc526 tm52 operating mode selection 0 1 clears and starts on match between tm52 and cr52. pwm (free-running) mode tmc524 single mode/cascade mode selection 0 1 single mode cascade mode (connected to tm51) lvs52 timer output f/f status setting of 8-bit timer/event counter 52 0 0 not affected resets timer output f/f (to 0). tmc521 other than pwm mode (tmc526 = 0) 0 1 disables inverted operation. enables inverted operation. toe52 timer output control of 8-bit timer/event counter 52 0 1 disables output (port mode). enables output. ff78h 00h r/w 54 symbol address after reset r/w lvs52 76 32 0 1 tce52 tmc524 lvr52 0 1 1 sets timer output f/f (to 1). 0 1 setting prohibited 1 pwm mode (tmc526 = 1) timer f/f control active level selection high active low active chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 146 (2) timer clock select registers 50, 51, and 52 (tcl50, tcl51, and tcl52) these registers specify the count clock of 8-bit timer counters 50, 51, and 52 (tm50, tm51, and tm52) and the valid edges of the ti50, ti51, and ti52 inputs. tcl50, tcl51, and tcl52 are set by an 8-bit memory manipulation instruction. reset input clears these registers to 00h. figures 7-7 to 7-9 show the formats of tcl50, tcl51, and tcl52. figure 7-7. format of timer clock select register 50 note expanded-specification products only. cautions 1. before rewriting the data of tcl50, stop the timer operation once. 2. be sure to clear bits 3 to 7 of tcl50 to 0. remark f x : system clock oscillation frequency 000 tcl502 tcl501 tcl500 tcl50 ff71h 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 0 tcl502 tcl501 count clock selection 0 0 0 0 f x /2 7 f x /2 9 0 0 1 1 1 1 1 1 0 0 1 1 f x /2 11 falling edge of ti50 rising edge of ti50 93.7 khz 23.4 khz 5.85 khz 65.5 khz f x /2 5 375 khz 262 khz f x /2 3 1.5 mhz 1.05 mhz f x /2 6 mhz 4.19 mhz 16.4 khz 4.09 khz at f x = 12 mhz note at f x = 8.38 mhz tcl500 0 1 0 1 0 1 0 1 chapter 7 8-bit timer/event counter 147 user? manual u13029ej7v1ud figure 7-8. format of timer clock select register 51 note expanded-specification products only. cautions 1. before rewriting the data of tcl51, stop the timer operation once. 2. be sure to clear bits 3 to 7 of tcl51 to 0. remarks 1. f x : system clock oscillation frequency 2. the settings of tcl510 to tcl512 are invalid when tm50 and tm51 are connected in cascade. figure 7-9. format of timer clock select register 52 note expanded-specification products only. cautions 1. before rewriting the data of tcl52, stop the timer operation once. 2. be sure to clear bits 3 to 7 of tcl52 to 0. remarks 1. f x : system clock oscillation frequency 2. the settings of tcl520 to tcl522 are invalid when tm51 and tm52 are connected in cascade. 000 tcl512 tcl511 tcl510 tcl51 ff75h 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 0 tcl512 tcl511 count clock selection 0 0 0 0 f x /2 3 f x /2 4 0 0 1 1 1 1 1 1 0 0 1 1 f x /2 5 falling edge of ti51 rising edge of ti51 1.5 mhz 750 khz 375 khz 1.05 mhz f x /2 2 3 mhz 2.1 mhz f x /2 6 mhz 4.19 mhz f x 12 mhz 8.38 mhz 524 khz 262 khz at f x = 12 mhz note at f x = 8.38 mhz tcl510 0 1 0 1 0 1 0 1 000 tcl522 tcl521 tcl520 tcl52 ff79h 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 0 tcl522 tcl521 count clock selection 0 0 0 0 f x /2 7 f x /2 8 0 0 1 1 1 1 1 1 0 0 1 1 f x /2 9 falling edge of ti52 rising edge of ti52 93.7 khz 46.8 khz 23.4 khz 65.5 khz f x /2 6 187 khz 131 khz f x /2 5 375 khz 262 khz f x /2 4 750 khz 524 khz 32.7 khz 16.4 khz at f x = 12 mhz note at f x = 8.38 mhz tcl520 0 1 0 1 0 1 0 1 chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 148 (3) port mode register 2 (pm2) this register sets port 2 in the input or output mode in 1-bit units. when the p24/ti50/to50 to p26/ti52/to52 pins are used for timer output, clear pm24 to pm26 and the output latches of p24 to p26 to 0. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 7-10. format of port mode register 2 1 pm26 pm25 pm22 pm21 pm20 pm2 pm2n p2n pin i/o mode selection (n = 0 to 6) 0 1 output mode (output buffer on) input mode (output buffer off) ff22h ffh r/w 54 symbol address after reset r/w pm23 76 32 0 1 pm24 chapter 7 8-bit timer/event counter 149 user? manual u13029ej7v1ud 7.5 operation of 8-bit timer/event counter 7.5.1 interval timer (8-bit) operation the 8-bit timer/event counters operate as interval timers that repeatedly generate an interrupt request at time intervals specified by the count values preset to corresponding 8-bit compare register 5n (cr5n). when the count values of 8-bit timer counter 5n (tm5n) match the values set to corresponding compare register cr5n, the value of tm5n is cleared to 0, tm5n continues counting, and at the same time, an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected by bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). for the operation to be performed when the value of the compare register is changed during timer count operation, refer to 7.6 notes on 8-bit timer/event counter (2) . chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 150 figure 7-11. interval timer operation timing (2/3) (b) when cr5n = 00h (c) when cr5n = ffh remark n = 0 to 2 t count clock tm5n cr5n tce5n 00h 00h 00h 00h 00h inttm5n to5n interval time t interval time count clock tm5n cr5n inttm5n to5n ffh ffh ffh interrupt request acknowledged interrupt request acknowledged 01h feh ffh 00h feh 00h tce5n ffh chapter 7 8-bit timer/event counter 151 user? manual u13029ej7v1ud figure 7-11. interval timer operation timing (3/3) (d) operation when cr5n is changed (m < n) (e) operation when cr5n is changed (m > n) remark n = 0 to 2 change of cr5n count clock tm5n cr5n inttm5n to5n nm 00h m ffh n 00h m tce5n 00h n tm5n overflows because m < n. h change of cr5n count clock tm5n cr5n inttm5n to5n nm n ?1 00h m ?1 00h tce5n 01h n 01h n m h chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 152 7.5.2 external event counter operation the external event counter counts the number of clock pulses externally input to the ti50/p24 to ti52/p26 pins by using 8-bit timer counter 5n (tm5n). each time the valid edge specified by timer clock select register 5n (tcl5n) is input, the value of tm5n is incremented. either the rising edge or falling edge can be specified as the valid edge. when the count value of tm5n matches the values of corresponding 8-bit compare register 5n (cr5n), tm5n is cleared to 0, and an interrupt request signal (inttm5n) is generated. whenever the tm5n value matches the value of cr5n, inttm5n is generated. remark n = 0 to 2 figure 7-12. external event counter operation timing (with rising edge specified) remark n = 00h to ffh n = 0 to 2 ti5n pin input tm5n count value 00h 01h 05h 03h 01h 03h cr5n n inttm5n 04h 02h 02h n ?1 n 00h chapter 7 8-bit timer/event counter 153 user? manual u13029ej7v1ud 7.5.3 square-wave output (8-bit resolution) operation the 8-bit timer/event counters operate as a square wave output at the interval preset to 8-bit compare register 5n (cr5n). when bit 0 (toe5n) of 8-bit timer mode control register 5n (tmc5n) is set to 1, the output status of to5n is inverted at the interval time specified by the count value preset to cr5n. in this way, a square-wave of any frequency (duty factor = 50%) can be output. chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 154 7.5.4 8-bit pwm output operation the pwm output operation is performed when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. a pulse with a duty factor determined by the value set to 8-bit compare register 5n (cr5n) is output from to5n. set the width of the active level of the pwm pulse to cr5n. the active level can be selected using bit 1 (tmc5n1) of tmc5n. the count clock can be selected by bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). pwm output can be enabled or disabled by bit 0 (toe5n) of tmc5n. (1) basic operation of pwm output chapter 7 8-bit timer/event counter 155 user? manual u13029ej7v1ud figure 7-14. pwm output operation timing (a) basic operation (when active level = h) (b) when cr5n = 0 (c) when cr5n = ffh remark n = 0 to 2 active level count clock tm5n cr5n inttm5n to5n n 01h 00h 01h 02h n + 1 ffh tce5n n 00h 01h 02h m inactive level active level 00h ffh 00h count clock tm5n cr5n inttm5n to5n 00h 01h 00h 01h 02h n + 1 ffh tce5n n 00h 01h 02h m 00h ffh 00h n + 2 inactive level inactive level l active level count clock tm5n cr5n inttm5n to5n ffh 01h 00h 01h 02h n + 1 ffh tce5n n 00h 01h 02h m inactive level active level 00h ffh 00h n + 2 inactive level inactive level chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 156 (2) operation when cr5n is changed figure 7-15. operation timing when cr5n is changed (a) if value of cr5n is changed from n to m before tm5n overflows (b) if value of cr5n is changed from n to m after tm5n overflows (c) if value of cr5n is changed from n to m within 2 clocks (00h, 01h) immediately after tm5n overflows remark n = 0 to 2 change of cr5n (n m) count clock tm5n cr5n inttm5n to5n n n + 2 ffh 00h 01h m m + 1 tce5n m + 2 ffh 02h 00h n 02h 01h n + 1 mm + 1 m + 2 m h change of cr5n (n m) count clock tm5n cr5n inttm5n to5n n n + 2 ffh 00h 01h n n + 1 tce5n n + 2 ffh 02h 00h n 02h 01h n + 1 mm + 1 m + 2 n h 03h m change of cr5n (n m) count clock tm5n cr5n inttm5n to5n n n + 2 ffh 00h 01h n n + 1 tce5n n + 2 ffh 02h 00h n 02h 01h n + 1 mm + 1 m + 2 n h m chapter 7 8-bit timer/event counter 157 user? manual u13029ej7v1ud 7.5.5 interval timer (16-bit) operation (1) cascade (16-bit timer) mode (tm50 and tm51) the 16-bit resolution timer/event counter mode is set by setting bit 4 (tmc514) of 8-bit timer mode control register 51 (tmc51) to 1. in this mode, tm50 and tm51 operate as a 16-bit interval timer that repeatedly generates an interrupt request at intervals specified by the count value preset to 8-bit compare registers 50 and 51 (cr50 and cr51). chapter 7 8-bit timer/event counter user? manual u13029ej7v1ud 158 (2) cascade (16-bit timer) mode (tm51 and tm52) the 16-bit resolution timer/event counter mode is set by setting bit 4 (tmc524) of 8-bit timer mode control register 52 (tmc52) to 1. in this mode, tm51 and tm52 operate as a 16-bit interval timer that repeatedly generates an interrupt request at intervals specified by the count value preset to 8-bit compare registers 51 and 52 (cr51 and cr52). chapter 7 8-bit timer/event counter 159 user? manual u13029ej7v1ud 7.6 notes on 8-bit timer/event counter (1) error on starting timer an error of up to 1 clock occurs after the timer has been started until a match signal is generated. this is because 8-bit timer counter 5n (tm5n: n = 0 to 2) is started asynchronously to the count clock. figure 7-18. start timing of 8-bit timer counter remark n = 0 to 2 (2) operation after changing value of compare register during timer count operation if the new value of 8-bit compare register 5n (cr5n: n = 0 to 2) is less than the value of corresponding 8-bit timer counter 5n (tm5n: n = 0 to 2), tm5n continues counting, overflows, and restarts counting from 0. therefore, if the new value of cr5n (m) is less than the old value (n), it is necessary to restart the timer after changing the value of cr5n. figure 7-19. timing after changing values of compare registers during timer count operation caution except when ti5n input is selected, be sure to clear tce5n to 0 before setting the stop mode. remark n > x > m n = 0 to 2 (3) reading tm5n during timer operation because the count clock is stopped when tm5n is read during operation, select a count clock with a waveform whose high-/low-level is longer than two cpu clock cycles. for example, in the case of a cpu clock (f cpu ) equal to f x , tm5n can be read as long as the selected count clock is f x /4 or lower. remark n = 0 to 2 f x : system clock oscillation frequency count clock tm5n count value timer starts 00h 01h 02h 03h 04h count clock cr5n n m tm5n count value x ?1 x ffh 00h 01h 02h user? manual u13029ej7v1ud 160 chapter 8 10-bit inverter control timer 8.1 outline of 10-bit inverter control timer the 10-bit inverter control timer makes inverter control possible. it consists of an 8-bit dead-time generation timer, and allows non-overlapping active-level output. 8.2 function of 10-bit inverter control timer the 10-bit inverter control timer realizes inverter control. it incorporates an 8-bit timer for dead time generation and can output waveforms that do not overlap active levels. a total of six positive phase and negative phase channels are output. in addition, an active level change function and output off function by external input (toff7) or watchdog timer interrupt request input are provided. 8.3 configuration of 10-bit inverter control timer the 10-bit inverter control timer includes the following hardware. table 8-1. configuration of 10-bit inverter control timer item function timer counter 10-bit up/down counter 1 (tm7) dead-time timers 3 (dtm0, dtm1, dtm2) buffer transfer control timer 1 (rtm0) registers 10-bit compare registers 4 (cm0, cm1, cm2, cm3) 10-bit buffer registers 4 (bfcm0, bfcm1, bfcm2, bfcm3) dead-time reload register 1 (dtime) timer outputs 6 (to70, to71, to72, to73, to74, to75) control registers inverter timer control register 7 (tmc7) inverter timer mode register 7 (tmm7) chapter 8 10-bit inverter control timer 161 user? manual u13029ej7v1ud figure 8-1. block diagram of 10-bit inverter control timer (1) 10-bit up/down counter (tm7) tm7 is a 10-bit up/down counter that counts count pulses in synchronization with the rising edge of the count clock. when the timer starts, the number of count pulse count is incremented from 0, and when the value preset to compare register 3 (cm3) and tm7 count value match, it is switched to the count down operation. an underflow signal is generated if the value becomes 000h during the count down operation and interrupt request signal inttm7 is generated. when an underflow occurs, it is switched from the count down operation to the count up operation. inttm7 is normally generated at every underflow but the number of occurrences can be divided by the idev0 to idev2 bits of inverter timer control register 7 (tmc7). tm7 cannot be read/written. the cycle of tm7 is controlled by cm3. the count clock can be selected from 6 types: f x , f x /2, f x /4, f x /8, f x /16, f x /32. reset input or clearing the ce7 bit of tmc7 sets tm7 to 000h. (2) 10-bit compare registers 0 to 2 (cm0 to cm2) cm0 to cm2 are 10-bit compare registers that always compare their own value with that of tm7, and if they match, the contents of the flip-flops are changed. each of cm0 to cm2 are provided with a buffer register (bfcm0 to bfcm2), so that the contents of the buffer can be transferred to cm0 to cm2 at the timing of interrupt request signal inttm7 generation. a write operation to cm0 to cm2 is possible only while tm7 is stopped. to set the output timing, write data to bfcm0 to bfcm3. reset input or clearing the ce7 bit of tmc7 sets these registers to 000h. f x /2 5 f x /2 4 f x /2 3 f x /2 2 f x /2 f x tm7 inttm7 10 cm3 bfcm3 cm0 bfcm0 cm1 bfcm1 cm2 bfcm2 dtime dtm0 dtm1 dtm2 8 f x pulse generator output off function by external input (toff7) or intwdt to70 (u phase) to71 (u phase) to72 (v phase) to73 (v phase) to74 (w phase) to75 (w phase) rtm0 chapter 8 10-bit inverter control timer user? manual u13029ej7v1ud 162 (3) 10-bit compare register 3 (cm3) cm3 is a 10-bit compare register that controls the high limit value of tm7. if the count value of tm7 matches the value of cm3 or 0, count up/down is switched at the next count clock. cm3 provides a buffer register (bfcm3) whose contents are transferred to cm3 at the timing of interrupt request signal inttm7 generation. cm3 can be written to only while tm7 is stopped. to set the cycle to tm7, write data to bfcm3. reset input sets cm3 to 0ffh. do not set cm3 to 000h. (4) 10-bit buffer registers 0 to 3 (bfcm0 to bfcm3) bfcm0 to bfcm3 are 10-bit registers. they transfer data to the compare register (cm0 to cm3) corresponding to each buffer register at the timing of interrupt request signal inttm7 generation. bfcm0 to bfcm3 can be read/written irrespective of whether tm7 count is stopped or operating. reset input sets bfcm0 to bfcm2 to 000h, and bfcm3 to 0ffh. these registers can be read/written in word and byte units. for read/write operations of less than 8 bits, bfcm0l to bfcm3l are used. (5) dead-time reload register (dtime) dtime is an 8-bit register to set dead time and is common to three dead-time timers (dtm0 to dtm2). however, the data load timing from dtime to dtm0, dtm1 and dtm2 is independent. dtime can be written only while tm7 counting is stopped. data does not change even if an instruction to rewrite dtime is executed during timer operation. reset input sets dtime to ffh. even if dtime is set to 00h, an output with the dead time of f x is performed. (6) dead-time timers 0 to 2 (dtm0 to dtm2) dtm0 to dtm2 are 8-bit down counters that generate dead time. count down is performed after the value of the dead-time reload register (dtime) is reloaded with the timing of a compare match between cm0 to cm2 and tm7. dtm0 to dtm2 generate an underflow signal when 00h changes to ffh and stop with ffh. the count clock is f x . dtm0 to dtm2 cannot be read/written. reset input or clearing the ce7 bit of tmc7 sets these registers to ffh. (7) buffer transfer control timer (rtm0) rtm0 is a 3-bit up counter. it has the function of dividing interrupt request signal inttm7. incrementing is performed with the tm7 underflow signal and inttm7 is generated when the value matches the number of divisions set with bits idev0 to idev2 of tmc7. rtm0 cannot be read/written. reset input sets rtm0 to 7h. generating inttm7 and clearing the ce7 bit of tmc7 also sets rtm0 to 7h. chapter 8 10-bit inverter control timer 163 user? manual u13029ej7v1ud 8.4 registers controlling 10-bit inverter control timer the following two registers control the 10-bit inverter control timer. ?inverter timer control register 7 (tmc7) ?inverter timer mode register 7 (tmm7) (1) inverter timer control register 7 (tmc7) tmc7 controls the operation of tm7, dead-time timers 0 to 2 (dtm0 to dtm2), and the buffer transfer control timer (rtm0), specifies the count clock of tm7, and selects the compare register transfer cycle. tmc7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc7 to 00h. chapter 8 10-bit inverter control timer user? manual u13029ej7v1ud 164 figure 8-2. format of inverter timer control register 7 note expanded-specification products only. remark f x : system clock oscillation frequency ce7 0 tcl72 tcl71 tcl70 idev2 idev1 idev0 76 43210 ff90h address tmc7 symbol 5 00h after reset r/w r/w ce7 0 1 tm7, dtm0 to dtm2, rtm0 operation control clear and stop (to70 to to75 are hi-z) count enable idev2 0 0 0 0 1 1 1 1 idev1 0 0 1 1 0 0 1 1 idev0 0 1 0 1 0 1 0 1 inttm7 occurrence frequency selection occurs once every tm7 underflow. occurs once every two tm7 underflows. occurs once every three tm7 underflows. occurs once every four tm7 underflows. occurs once every five tm7 underflows. occurs once every six tm7 underflows. occurs once every seven tm7 underflows. occurs once every eight tm7 underflows. tcl72 tcl71 count clock selection 0 0 0 0 f x /2 3 f x /2 4 0 0 1 1 1 1 0 0 f x /2 5 setting prohibited 1.5 mhz 750 khz 375 khz 1.05 mhz f x /2 2 3 mhz 2.1 mhz f x /2 6 mhz 4.19 mhz f x 12 mhz 8.38 mhz 524 khz 262 khz at f x = 12 mhz note at f x = 8.38 mhz tcl70 0 1 0 1 0 1 other than above chapter 8 10-bit inverter control timer 165 user? manual u13029ej7v1ud (2) inverter timer mode register 7 (tmm7) tmm7 controls the operation of and specifies the active level of the to70 to to75 outputs, and sets the valid edge of toff7. tmm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmm7 to 00h. figure 8-3. format of inverter timer mode register 7 note the pnoffb bit is a read-only flag. this bit cannot be set or reset by software. pnoffb is reset when an output stop is generated by toff7 and intwdt while tm7 is stopped (ce7 = 0) or operating (ce7 = 1). caution always set bits 5 to 7 of tmm7 to 0. 000 pnoffb alv toedg tospp tospw 76 43210 ff91h address tmm7 symbol 5 00h after reset r/w r/w pnoffb 0 1 control status flag of tm7 output to to70 to to75 tm7 output disabled status (to70 to to75 are hi-z) tm7 output enabled status alv 0 1 to70 to to75 output active level specification low level high level toedg 0 1 toff7 valid edge specification falling edge rising edge tospp 0 1 to70 to to75 output stop control by valid edge of toff7 output not stopped. output stopped (to70 to to75 are hi-z). tospw 0 1 to70 to to75 output stop control by intwdt output not stopped. output stopped (to70 to to75 are hi-z). note note chapter 8 10-bit inverter control timer user? manual u13029ej7v1ud 166 remarks 1. to70 to to75 become hi-z state in the following cases. however, the tm7, dtm0 to dtm2, and rtm0 timers do not stop if ce7 = 1 is set. ?a valid edge is input to the toff7 pin while tospp = 1. ?a specified interrupt request is generated while tospw = 1. to restore the output of to70 to to75, perform the procedure below. <1> write 0 to ce7 and stop the timer. <2> write 0 to the output stop function flag that is used. <3> reset the registers to their default values. 2. pnoffb, alv, ce7, and to70 to to75 are related as follows. pnoffb alv ce7 to70, to72, to74 to71, to73, to75 00 0 hi-z hi-z 01 0 hi-z hi-z 0 0/1 1 hi-z hi-z 1 0/1 1 pwm wave output pwm wave output chapter 8 10-bit inverter control timer 167 user? manual u13029ej7v1ud 8.5 operation of 10-bit inverter control timer (1) setting procedure (a) the tm7 count clock is set with the tcl70 to tcl72 bits of inverter timer control register 7 (tmc7) and the occurrence frequency of interrupt request signal inttm7 is set with the idev0 to idev2 bits. (b) the active level of the to70 to to75 pins is set with the alv bit of inverter timer mode register 7 (tmm7). (c) set the half width of the first pwm cycle to 10-bit compare register 3 (cm3). ? wm cycle = cm3 value 2 tm7 clock rate (the clock rate of tm7 is set with the tmc7) (d) set the half width of the second pwm cycle to 10-bit buffer register 3 (bfcm3). (e) set the dead time width to the dead time reload register (dtime). dead time width = (dtime + 1) f x f x : internal system clock (f) set the f/f set/reset timing that is used during the first cycle to 10-bit compare registers 0 to 2 (cm0 to cm2). (g) set the f/f set/reset timing that is used during the second cycle to bfcm3. (h) after the ce7 bit of tmc7 is set (1), the operation of tm7, dead-time timers 0 to 2 (dtm0 to dtm2), and buffer transfer control timer (rtm0) is enabled. caution always use a bit manipulation instruction to set the ce7 bit. (i) set the f/f set/reset timing that is used for the next cycle to bfcm0 to bfcm3 during tm7 operation. (j) to stop the tm7 operation, set the ce7 bit of the tmc7 to 0. caution another bit cannot be rewritten at the same time that the ce7 bit is being rewritten. chapter 8 10-bit inverter control timer user? manual u13029ej7v1ud 168 (2) output waveform widths corresponding to set values ? wm cycle = cm3 2 t tm7 dead-time width = t dtm = (dtime + 1) f x active width of positive phase (to70, to72, to74 pin) = {(cm3 ?cm up ) + (cm3 ?cm down )} t tm7 ?t dtm active width of negative phase (to71, to73, to75 pin) = (cm down + cm up ) t tm7 ?t dtm f x : system clock oscillation frequency t tm7 : tm7 count clock cm up : set value of cm0 to cm2 during tm7 count up cm down : set value of cm0 to cm2 during tm7 count down caution if a value whose active width in the positive phase or negative phase becomes 0 or negative via the above calculation, to70 to to75 output a waveform fixed at the inactive level with an active width of 0 (refer to figure 8-5). however, if cmn = 0 and bfcmn cm3 are set, to70 to to75 output a waveform at the active level. chapter 8 10-bit inverter control timer 169 user? manual u13029ej7v1ud (3) operation timing figure 8-4. tm7 operation timing (basic operation) remarks 1. n = 0 to 2 2. t: dead time = (dtime + 1) f x (f x : system clock oscillation frequency) 3. the above figure assumes an active high and undivided inttm7 occurrence. x 0 b aa y c b a c yz x tt bb tt yz inttm7 inttm7 tm7 bfcmn cmn bfcm3 cm3 f/f dtmn to70, to72, to74 to71, to73, to75 chapter 8 10-bit inverter control timer user? manual u13029ej7v1ud 170 figure 8-5. tm7 operation timing (cmn (bfcmn) cm3 (bfcm3)) remarks 1. n = 0 to 2 2. t: dead time = (dtime + 1) f x (f x : system clock oscillation frequency) 3. the above figure assumes an active high and undivided inttm7 occurrence. if a value higher than cm3 is set to bfcmn, low-level output in the positive phases (to70, to72, to74 pins), and high-level output in the negative phases (to71, to73, to75 pins) are continued. this setting is effective to output signals whose low and high widths are longer than the pwm cycle when controlling an inverter, etc. x 0 b aa y c b ( y) a c yz x tt yz inttm7 inttm7 tm7 bfcmn cmn bfcm3 cm3 f/f dtmn to70, to72, to74 to71, to73, to75 chapter 8 10-bit inverter control timer 171 user? manual u13029ej7v1ud figure 8-6. tm7 operation timing (cmn (bfcmn) = 000h) remarks 1. n = 0 to 2 2. t: dead time = (dtime + 1) f x (f x : system clock oscillation frequency) 3. the above figure assumes an active high and undivided inttm7 occurrence. x 0 b aa z cc y c (> 0) d ab = 00h c d yz x t t tt yz z inttm7 inttm7 inttm7 tm7 bfcmn cmn bfcm3 cm3 f/f dtmn to70, to72, to74 to71, to73, to75 chapter 8 10-bit inverter control timer user? manual u13029ej7v1ud 172 figure 8-7. tm7 operation timing (cmn (bfcmn) = cm3 ?1/2dtm, cmn (bfcmn) > cm3 ?1/2dtm) remarks 1. n = 0 to 2 2. the above figure assumes an active high and undivided inttm7 occurrence. x 0 b aa bb y c a (= x ??tm) b (> y ??tm) c yz xyz inttm7 inttm7 tm7 bfcmn cmn bfcm3 cm3 f/f dtmn to70, to72, to74 to71, to73, to75 1 2 1 2 173 user? manual u13029ej7v1ud chapter 9 watchdog timer 9.1 outline of watchdog timer the watchdog timer can also be used to generate a non-maskable interrupt request, maskable interrupt request, or reset signal at preset time intervals. 9.2 function of watchdog timer the watchdog timer has the following functions. watchdog timer interval timer oscillation stabilization time specification caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (the watchdog timer and interval timer cannot be used simultaneously.) (1) watchdog timer mode the watchdog timer is used to detect an inadvertent program loop. when a loop is detected, a non-maskable interrupt request or the reset signal can be generated. table 9-1. loop detection time of watchdog timer loop loop detection time detection time 2 12 1/f x 341.3 s 488.8 s2 16 1/f x 5.46 ms 7.82 ms 2 13 1/f x 682.6 s 977.6 s2 17 1/f x 10.9 ms 15.6 ms 2 14 1/f x 1.36 ms 1.96 ms 2 18 1/f x 21.8 ms 31.3 ms 2 15 1/f x 2.73 ms 3.91 ms 2 20 1/f x 87.3 ms 125.1 ms note expanded-specification products only. remark f x : system clock oscillation frequency at f x = 12 mhz note at f x = 8.38 mhz at f x = 12 mhz note at f x = 8.38 mhz chapter 9 watchdog timer user? manual u13029ej7v1ud 174 (2) interval timer mode when the watchdog timer is used as an interval timer, it generates an interrupt request at preset time intervals. table 9-2. interval time interval time interval time 2 12 1/f x 341.3 s 488.8 s2 16 1/f x 5.46 ms 7.82 ms 2 13 1/f x 682.6 s 977.6 s2 17 1/f x 10.9 ms 15.6 ms 2 14 1/f x 1.36 ms 1.96 ms 2 18 1/f x 21.8 ms 31.3 ms 2 15 1/f x 2.73 ms 3.91 ms 2 20 1/f x 87.3 ms 125.1 ms note expanded-specification products only. remark f x : system clock oscillation frequency 9.3 configuration of watchdog timer the watchdog timer includes the following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) oscillation stabilization time select register (osts) figure 9-1. watchdog timer block diagram at f x = 12 mhz note at f x = 8.38 mhz at f x = 12 mhz note at f x = 8.38 mhz internal bus 3 clock input controller f x /2 8 f x run divider intwdt reset wdt mode signal osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 run wdtm4 wdtm3 division clock selector output controller division mode selector oscillation stabilization time select register (osts) watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) chapter 9 watchdog timer 175 user? manual u13029ej7v1ud 9.4 registers controlling watchdog timer the following three registers control the watchdog timer. watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) oscillation stabilization time select register (osts) (1) watchdog timer clock select register (wdcs) (refer to figure 9-2) this register sets the overflow time of watchdog timer and interval timer. wdcs is set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-2. format of watchdog timer clock select register note expanded-specification products only. remark f x : system clock oscillation frequency 6543210 7 symbol wdcs 0 0 0 0 0 wdcs2 wdcs1 wdcs0 0 0 watchdog timer/interval timer overflow time selection 2 12 /f x 2 14 /f x 0 0 1 1 1 1 ff42h 00h r/w address after reset r/w wdcs2 0 0 1 1 0 0 1 1 wdcs1 0 1 1 0 0 1 0 1 wdcs0 2 13 /f x 2 15 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 20 /f x 488.8 s 977.6 s 3.91 ms 1.96 ms 7.82 ms 15.6 ms 31.3 ms 125.1 ms 341.3 s 682.6 s 2.73 ms 1.36 ms 5.46 ms 10.9 ms 21.8 ms 87.3 ms at f x = 12 mhz note at f x = 8.38 mhz chapter 9 watchdog timer user? manual u13029ej7v1ud 176 (2) watchdog timer mode register (wdtm) this register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. wdtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-3. format of watchdog timer mode register notes 1. once wdtm3 and wdtm4 have been set to 1, they cannot be cleared to 0 by software. 2. the watchdog timer starts operating as an interval timer as soon as the run bit has been set to 1. 3. once run has been set to 1, it cannot be cleared to 0 by software. therefore, when counting is started, it cannot be stopped by any means other than reset input. caution when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 2 8 /f x seconds shorter than the time set by the watchdog timer clock select register (wdcs). remark : don? care 6543210 symbol wdtm run 0 0 wdtm 4 wdtm 3 000 wdtm4 0 selection of operation mode of watchdog timer note 1 and control of reset by watchdog timer and timer interrupt interval timer mode note 2 (overflow and maskable interrupt request occur)/pwm output off function of tm7 by intwdt can be used. 1 watchdog timer mode 2 (overflow occurs and reset operation started) stops counting. 1 watchdog timer mode 1 (overflow and non-maskable interrupt request occur)/pwm output off function of tm7 by intwdt can be used. selection of watchdog timer operation note 3 run 0 clears counter and starts counting. 1 fff9h 00h r/w address after reset r/w 1 0 wdtm3 7 chapter 9 watchdog timer 177 user? manual u13029ej7v1ud (3) oscillation stabilization time select register (osts) this register selects the oscillation stabilization time that elapses after the reset signal is applied or the stop mode is released, until oscillation is stabilized. osts is set by an 8-bit memory manipulation instruction. reset input sets this register to 04h. therefore, to release the stop mode by inputting the reset signal, the time required to release the mode is 2 17 /f x . figure 9-4. format of oscillation stabilization time select register note expanded-specification products only. remark f x : system clock oscillation frequency 6543210 7 symbol osts 0 0 0 0 0 osts2 osts1 osts0 fffah 04h r/w address after reset r/w other than above setting prohibited 0 0 selection of oscillation stabilization time when stop mode is released 2 12 /f x 2 15 /f x 0 0 1 osts2 0 0 1 1 0 osts1 0 1 1 0 0 osts0 2 14 /f x 2 16 /f x 2 17 /f x 488.8 s 1.96 ms 7.82 ms 3.91 ms 15.6 ms 341.3 s 1.36 ms 5.46 ms 2.73 ms 10.9 ms at f x = 12 mhz note at f x = 8.38 mhz chapter 9 watchdog timer user? manual u13029ej7v1ud 178 9.5 operation of watchdog timer 9.5.1 operation as watchdog timer the watchdog timer detects an inadvertent program loop when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the loop detection time interval of the watchdog timer can be selected by bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the set loop detection time interval after the watchdog timer has been started. by setting run to 1, the watchdog timer can be cleared and made to start counting. if run is not set to 1 and the loop detection time is exceeded, the system is reset or a non-maskable interrupt request is generated by the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in the halt mode, but stops in the stop mode. therefore, set run to 1 before entering the stop mode to clear the watchdog timer, and then execute the stop instruction. cautions 1. the actual loop detection time may be up to 2 8 /f x seconds shorter than the set time. 2. the count operation of the watchdog timer is stopped when the subsystem clock is selected as the cpu clock. table 9-4. loop detection time of watchdog timer wdcs22 wdcs21 wdcs20 loop detection time at f x = 12 mhz note at f x = 8.38 mhz 00 0 2 12 1/f x 341.3 s 488.8 s 00 1 2 13 1/f x 682.6 s 977.6 s 01 0 2 14 1/f x 1.36 ms 1.96 ms 01 1 2 15 1/f x 2.73 ms 3.91 ms 10 0 2 16 1/f x 5.46 ms 7.82 ms 10 1 2 17 1/f x 10.9 ms 15.6 ms 11 0 2 18 1/f x 21.8 ms 31.3 ms 11 1 2 20 1/f x 87.3 ms 125.1 ms note expanded-specification products only. remark f x : system clock oscillation frequency chapter 9 watchdog timer 179 user? manual u13029ej7v1ud 9.5.2 operation as interval timer when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 0, the watchdog timer operates as an interval timer that repeatedly generates an interrupt request at time intervals specified by a preset count value. bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs) can be used to select the interval time of interval timer. when bit 7 (run) of wdtm is set to 1, the watchdog timer starts operating as an interval timer. in the interval timer mode, the interrupt mask flag (wdtmk) and priority specification flag (wdtpr) are valid, and a maskable interrupt request (intwdt) can be generated. the default priority of intwdt is set as the highest of all the maskable interrupt requests. the interval timer continues operation in the halt mode, but stops in the stop mode. therefore, set run to 1 before entering the stop mode to clear the interval timer, and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm has been set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set, unless the reset signal is input. 2. the interval time immediately after it has been set by wdtm may be up to 2 8 /f x seconds shorter than the set time. table 9-5. interval time of interval timer wdcs2 wdcs1 wdcs0 interval time at f x = 12 mhz note at f x = 8.38 mhz 00 0 2 12 1/f x 341.3 s 488.8 s 00 1 2 13 1/f x 682.6 s 977.6 s 01 0 2 14 1/f x 1.36 ms 1.96 ms 01 1 2 15 1/f x 2.73 ms 3.91 ms 10 0 2 16 1/f x 5.46 ms 7.82 ms 10 1 2 17 1/f x 10.9 ms 15.6 ms 11 0 2 18 1/f x 21.8 ms 31.3 ms 11 1 2 20 1/f x 87.3 ms 125.1 ms note expanded-specification products only. remark f x : system clock oscillation frequency user? manual u13029ej7v1ud 180 chapter 10 real-time output port 10.1 function of real-time output port data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupts or external interrupt request generation, then output externally. this is called the real-time output function. the pins that output data externally are called real-time output ports. by using the real-time output port, it is possible to output a signal with no jitter. therefore, this is most suitable for applications where an arbitrary pattern is output at an arbitrary interval (open-loop control of a stepper motor, etc.). also, it is possible to perform pwm modulation at a specified pin for the output pattern. the pd780988 subseries has the following 2 channels of real-time output ports on chip. it is possible to specify the real-time output port in 1-bit units. ? bits 1, or 4 bits 2 ?real-time output port 0 ? bits 1, or 4 bits 1 ?real-time output port 1 10.2 configuration of real-time output port a real-time output port includes the following hardware. table 10-1. configuration of real-time output port item configuration register real-time output buffer register n (rtbl0n, rtbh0n) control registers port mode register 3 (pm3) real-time output port mode register n (rtpm0n) real-time output port control register n (rtpc0n) dc control register n (dcctln) n = 0, 1 chapter 10 real-time output port 181 user? manual u13029ej7v1ud figure 10-1. block diagram of real-time output port (1/2) (a) real-time output port 0 (8 bits 1, or 4 bits 2) remark n = 0 to 7 internal bus rtpoe00 rtpeg00 byte00 extr00 output trigger controller real-time output port 0 output latch port 3 output latch pwm modulation intp2 (from outside) inttm000 (from tm00) inttm52 (from tm52) to50 (from tm50) rtp7 ????????????????????rtp0 p37/rtp7 ????????????????p30/rtp0 real-time output port control register 0 (rtpc00) real-time output buffer register 0 lower 4 bits (rtbl00) port mode register 3 (pm3) real-time output port mode register 0 (rtpm00) dc control register 0 (dcctl0) real-time output buffer register 0 higher 4 bits (rtbh00) 4 p37 ?????????????????????p30 p3n/rtpn pin output chapter 10 real-time output port user? manual u13029ej7v1ud 182 figure 10-1. block diagram of real-time output port (2/2) (b) real-time output port 1 (6 bits 1, or 4 bits 1) remark n = 0 to 5 internal bus rtpoe01 byte01 output trigger controller real-time output port 1 output latch pwm modulation inttm001 (from tm01) to7n (from tm7) to75 ?????????????to70 real-time output port control register 1 (rtpc01) real-time output buffer register 1 higher 4 bits (rtbh01) real-time output buffer register 1 lower 4 bits (rtbl01) real-time output port mode register 1 (rtpm01) dc control register 1 (dcctl1) 2 chapter 10 real-time output port 183 user? manual u13029ej7v1ud (1) real-time output buffer register 0 (rtbl00, rtbh00) this register consists of two 4-bit registers that hold output data in advance. the addresses of rtbl00 and rtbh00 are mapped individually in the special function register (sfr) area as shown in figure 10-2. when specifying 4 bits 2 channels as the operation mode, data is set individually in rtbl00 and rtbh00. the data of both rtbl00 and rtbh00 can be read all at once regardless of which address is specified. when specifying 8 bits 1 channel as the operation mode, data is set to both rtbl00 and rtbh00 by writing 8-bit data to either rtbl00 or rtbh00. the data of both rtbl00 and rtbh00 can be read all at once regardless of which address is specified. figure 10-2 shows the configuration of rtbl00 and rtbh00, and table 10-2 shows operations during manipulation of rtbl00 and rtbh00. figure 10-2. configuration of real-time output buffer register 0 table 10-2. operation during manipulation of real-time output buffer register 0 reading note 1 writing note 2 higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl00 rtbh00 rtbl00 invalid rtbl00 rtbh00 rtbh00 rtbl00 rtbh00 invalid rtbl00 rtbh00 rtbl00 rtbh00 rtbl00 rtbh00 rtbh00 rtbl00 rtbh00 rtbl00 notes 1. only the bits set in the real-time output port mode can be read. when a bit set in the port mode is read, 0 is read. 2. after setting data in the real-time output port, output data should be set in rtbl00 and rtbh00 by the time a real-time output trigger is generated. operating mode register to be manipulated 4 bits 2 channels 8 bits 1 channel higher 4 bits lower 4 bits rtbl00 rtbh00 ff84h ff85h chapter 10 real-time output port user? manual u13029ej7v1ud 184 (2) real-time output buffer register 1 (rtbl01, rtbh01) this register consists of two 4-bit note registers that hold output data in advance. the addresses of rtbl01 and rtbh01 are mapped individually in the special function register (sfr) area as shown in figure 10-3. when specifying 4 bits 1 channel as the operation mode, data is set in rtbl01. when specifying 6 bits 1 channel as the operation mode, data is set to both rtbl01 and rtbh01 by writing 6-bit data to either rtbl01 or rtbh01. the data of both rtbl01 and rtbh01 can be read all at once regardless of which address is specified. figure 10-3 shows the configuration of rtbl01 and rtbh01, and table 10-3 shows operations during manipulation of rtbl01 and rtbh01. note for rtbh01, only 2 of the 4 bits are valid. figure 10-3. configuration of real-time output buffer register 1 table 10-3. operation during manipulation of real-time output buffer register 1 reading note 1 writing note 2 higher 2 bits lower 4 bits higher 2 bits lower 4 bits 4 bits 1 channel rtbl01 invalid rtbl01 invalid rtbl01 6 bits 1 channel rtbl01 rtbh01 rtbl01 rtbh01 rtbl01 rtbh01 rtbh01 rtbl01 rtbh01 rtbl01 notes 1. only the bits set in the real-time output port mode can be read. when the bit specified as rtpm01n = 0 (rtpm01n: bit n (n = 0 to 5) of real-time output port mode register 1 (rtpm01)) is read, 0 is read. 2. after setting data in the real-time output port, output data should be set in rtbl01 and rtbh01 by the time a real-time output trigger is generated. operating mode register to be manipulated higher 2 bits lower 4 bits rtbl01 rtbh01 ff9ch ff9dh chapter 10 real-time output port 185 user? manual u13029ej7v1ud 10.3 registers controlling real-time output port the following seven types of registers control the real-time output ports. port mode register 3 (pm3) real-time output port mode register 0, 1 (rtpm00, rtpm01) real-time output port control register 0, 1 (rtpc00, rtpc01) dc control register 0, 1 (dcctl0, dcctl1) (1) port mode register 3 (pm3) this register sets the input/output mode of port 3 pins (p30 to p37) that function alternately as real-time output pins (rtp0 to rtp7). to use port 3 as a real-time output port, the input/output mode of the port pins used as real-time output port pins must be set in the output mode (pm3n = 0: n = 0 to 7). pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 10-4. format of port mode register 3 (2) real-time output port mode register 0 (rtpm00) this register sets the real-time output port mode or port mode in 1-bit units. the output is rtp0 to rtp7. rtpm00 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-5. format of real-time output port mode register 0 caution when using a port as a real-time output port, set the port in the output mode (by clearing the corresponding bit of port mode register 3 (pm3) to 0). rtpm007 rtpm006 rtpm005 rtpm004 rtpm002 rtpm001 rtpm000 rtpm00 rtpm00n real-time output port selection (n = 0 to 7) 0 1 port mode real-time output port mode ff86h 00h r/w 54 symbol address after reset r/w rtpm003 76 32 0 1 pm37 pm36 pm35 pm34 pm32 pm31 pm30 pm3 pm3n p3n pin i/o mode selection (n = 0 to 7) 0 1 output mode (output buffer on) input mode (output buffer off) ff23h ffh r/w 54 symbol address after reset r/w pm33 76 32 0 1 chapter 10 real-time output port user? manual u13029ej7v1ud 186 (3) real-time output port mode register 1 (rtpm01) this register sets the real-time output port mode in 1-bit units. the output is to70 to to75. rtpm01 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-6. format of real-time output port mode register 1 caution be sure to set bit 6 and 7 of rtpm01 to 0. remark when using as a real-time output port, to70 to to75 become the output. 00 rtpm015 rtpm014 rtpm012 rtpm011 rtpm010 rtpm01 rtpm01n real-time output port selection (n = 0 to 5) 0 1 ??output real-time output port mode ff9eh 00h r/w 54 symbol address after reset r/w rtpm013 76 32 0 1 chapter 10 real-time output port 187 user? manual u13029ej7v1ud (4) real-time output port control register 0 (rtpc00) this register is used to set the operation mode, output trigger and operation enable/disable of the real-time output port. the output is rtp0 to rtp7. the relationship between the operation mode of the real-time output port and output trigger is as shown in table 10-4. rtpc00 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-7. format of real-time output port control register 0 note when rtpm00n (bit n (n = 0 to 7) of real-time output port mode register 0 (rtpm00)) is 1, inv0 (bit 4 of dc control register 0 (dcctl0)) is 0, and real-time output operation is disabled (rtpoe00 = 0), rtp0 to rtp7 output ?? table 10-4. real-time output port operation mode and output trigger byte00 extr00 operation mode rtbh00 port output rtbl00 port output 00 4 bits 2 channels inttm52 inttm000 01 inttm000 intp2 10 8 bits 1 channel inttm000 11 intp2 rtpoe00 rtpeg00 byte00 extr00 000 rtpc00 rtpoe00 real-time output port operation control 0 1 disables operation note enables operation rtpeg00 intp2 valid edge specification 0 1 falling edge rising edge byte00 real-time output port operation mode 0 1 4 bits 2 channels 8 bits 1 channel extr00 real-time output control by intp2 0 1 intp2 not used as real-time output trigger. intp2 used as real-time output trigger. ff87h 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 chapter 10 real-time output port user? manual u13029ej7v1ud 188 (5) real-time output port control register 1 (rtpc01) this register is used to set the operation mode, and enabling or disabling operation of the real-time output port. the output is to70 to to75. the relationship between the operation mode of the real-time output port and output trigger is as shown in table 10-5. rtpc01 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-8. format of real-time output port control register 1 note when rtpm01n (bit n (n = 0 to 5) of real-time output port mode register 1 (rtpm01)) is 1, inv1 (bit 4 of dc control register 1 (dcctl1)) is 0, and real-time output operation is disabled (rtpoe01 = 0), to70 to to75 output ?? table 10-5. real-time output port operation mode and output trigger byte01 operation mode rtbh01 port output rtbl01 port output 04 bits 1 channel inttm001 16 bits 1 channel inttm001 rtpoe01 0 byte01 0000 rtpc01 rtpoe01 real-time output port operation control 0 1 disables operation note enables operation byte01 real-time output port operation mode 0 1 4 bits 1 channel 6 bits 1 channel ff9fh 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 chapter 10 real-time output port 189 user? manual u13029ej7v1ud (6) dc control register 0 (dcctl0) this register is used to enable/disable pwm modulation, and enable/disable inversion of the output waveform of the real-time output port. the output is rtp0 to rtp7. dcctl0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-9. format of dc control register 0 note the pwm signal uses the to50 output. remarks 1. the output is rtp0 to rtp7. 2. the pwmch0, pwmcl0, and inv0 settings are valid only when dcen0 = 1. dcen0 pwmch0 pwmcl0 inv0 0 0 0 dcctl0 dcen0 output operation specification 0 1 rtp output pwm modulated rtp output note pwmch0 pwm modulation specification (rtp0, rtp2, rtp4 output specification) 0 1 pwm modulation disabled pwm modulation enabled pwmcl0 pwm modulation specification (rtp1, rtp3, rtp5 output specification) 0 1 pwm modulation disabled pwm modulation enabled inv0 output waveform specification 0 1 inversion disabled inversion enabled ffb8h 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 chapter 10 real-time output port user? manual u13029ej7v1ud 190 (7) dc control register 1 (dcctl1) this register is used to enable/disable pwm modulation, and enable/disable inversion of the output waveform of the real-time output port. the output is to70 to to75. dcctl1 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-10. format of dc control register 1 note the pwm signal uses the inverter timer output (to70 to to75). remarks 1. the output is to70 to to75. 2. the pwmch1, pwmcl1, and inv1 settings are valid only when dcen1 = 1. dcen1 pwmch1 pwmcl1 inv1 0 0 0 dcctl1 dcen1 output operation specification 0 1 inverter timer output (to70 to to75) pwm modulated rtp output note pwmch1 pwm modulation specification (to70, to72, to74 output specification) 0 1 pwm modulation disabled pwm modulation enabled pwmcl1 pwm modulation specification (to71, to73, to75 output specification) 0 1 pwm modulation disabled pwm modulation enabled inv1 output waveform specification 0 1 inversion disabled inversion enabled ffbch 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 chapter 10 real-time output port 191 user? manual u13029ej7v1ud 10.4 operation of real-time output port (1) using rtp0 to rtp7 as the real-time output port ..... real-time output port 0 (8 bits 1, or 4 bits 2) when bit 7 (rtpoe00) of real-time output port control register 0 (rtpc00) is 1, and real-time output operation is enabled, the data in real-time output buffer register 0 (rtbh00, rtbl00) is transferred to the output latch in synchronization with the generation of the selected transfer trigger (set by extr00 and byte00). of the transferred data, only the data of the bit specified for the real-time output port by setting real-time output port mode register 0 (rtpm00) is output from bits rtp0 to rtp7. the ports specified as port mode by rtpm00 can be used as general-purpose input/output ports. the operation mode can be selected as 8 bits 1, or 4 bits 2, by setting extr00 and byte00. by setting inv0, it is possible to invert the output waveform. also, by setting pwmcl0 and pwmch0, it is possible to perform pwm modulation of the output pattern. if real-time output was disabled (rtpoe00 = 0) when rtpm00n = 1 and inv0 = 0, then rtp0 to rtp7 output 0. the relationship between the settings for each bit of the control register and the real-time output is shown in table 10-6, and an example of the operation timing is shown in figure 10-11. remark extr00: bit 4 of real-time output port control register 0 (rtpc00) byte00: bit 5 of real-time output port control register 0 (rtpc00) inv0: bit 4 of dc control register 0 (dcctl0) pwmcl0, pwmch0: bits 5 and 6 of dc control register 0 (dcctl0) rtpm00n: bit n (n = 0 to 7) of real-time output port mode register 0 (rtpm00) chapter 10 real-time output port user? manual u13029ej7v1ud 192 table 10-6. relationship between settings of each bit of control register and real-time output pm3n p3n dcen0 inv0 pwmch0/ rtpoe00 rtpm00n rtbh00m/ pin p3n status pwmcl0 rtbl00m 1 input port 01 ?igh?output 00 0 ?ow?output 10 ?ow?output 10 ?ow?output 1 ?igh?output 1000 ?ow?output 10 ?ow?output 10 ?ow?output 1 ?igh?output 10 ?o50?output 10 ?o50?output 10 ?o50?output 1 ?igh?output 100 ?igh?output 10 ?igh?output 10 ?igh?output 1 ?ow?output 10 ?o50?output 10 ?o50?output 10 ?o50?output 1 ?ow?output pm3n: bit n of port mode register 3 (pm3) p3n: bit n of port 3 (p3) dcen0: bit 7 of dc control register 0 (dcctl0) inv0: bit 4 of dcctl0 pwmch0: bit 6 of dcctl0 pwmcl0: bit 5 of dcctl0 rtpoe00: bit 7 of real-time output port control register 0 (rtpc00) rtpm00n: bit n of real-time output port mode register 0 (rtpm00) rtbh00m: bit m of real-time output buffer register 0h (rtbh00) rtbl00m: bit m of real-time output buffer register 0l (rtbl00) n = 0 to 7 m = 0 to 3 : don? care chapter 10 real-time output port 193 user? manual u13029ej7v1ud figure 10-11. real-time output port operation timing example (8 bits 1) (1/3) (a) 8 bits 1 channel, inverted output disabled, no pwm modulation (extr00 = 0, byte00 = 1, inv0 = 0, pwmch0 = 0, pwmcl0 = 0) a: inttm000 software processing (rtbh00, rtbl00 write) inttm000 cpu operation a 01h 02h 03h 04h 05h 06h 07h 08h 09h 01h l l l l 02h 03h 04h 05h 06h 07h 08h 09h 0ah aaaaaaaaa rtbh00, rtbl00 output latch p30 output latch p31 output latch p32 output latch p33 output latch p34 output latch p35 output latch p36 output latch p37 output latch p30 to p37 chapter 10 real-time output port user? manual u13029ej7v1ud 194 figure 10-11. real-time output port operation timing example (8 bits 1) (2/3) (b) 8 bits 1 channel, inverted output enabled, no pwm modulation (extr00 = 0, byte00 = 1, inv0 = 1, pwmch0 = 0, pwmcl0 = 0) a: inttm000 software processing (rtbh00, rtbl00 write) a 01h 02h 03h 04h 05h 06h 07h 08h 09h 01h h h h h 02h 03h 04h 05h 06h 07h 08h 09h 0ah aaaaaaaaa inttm000 cpu operation rtbh00, rtbl00 output latch p30 output latch p31 output latch p32 output latch p33 output latch p34 output latch p35 output latch p36 output latch p37 output latch p30 to p37 chapter 10 real-time output port 195 user? manual u13029ej7v1ud figure 10-11. real-time output port operation timing example (8 bits 1) (3/3) (c) 8 bits 1 channel, inverted output enabled, pwm modulation (extr00 = 0, byte00 = 1, inv0 = 1, pwmch0 = 1, pwmcl0 = 1) a: inttm000 software processing (rtbh00, rtbl00 write) a 01h 02h 03h 04h 05h 06h 07h 08h 09h 01h h h h h 02h 03h 04h 05h 06h 07h 08h 09h 0ah aaaaaaaaa inttm000 cpu operation rtbh00, rtbl00 output latch p30 output latch p31 output latch p32 output latch p33 output latch p34 output latch p35 output latch p36 output latch p37 output latch p30 to p37 chapter 10 real-time output port user? manual u13029ej7v1ud 196 (2) using to70 to to75 as a real-time output port ..... real-time output port 1 (6 bits 1, or 4 bits 1) if real-time output is enabled when bit 7 (rtpoe01) of real-time output port control register 1 (rtpc01) is 1, the data of real-time output buffer register 1 (rtbh01, rtbl01) is transferred to the output latch in synchronization with the generation of inttm001. of the transferred data, only the data of the bit specified as the real-time output port by setting real-time output port mode register 1 (rtpm01) is output from bits to70 to to75. it is possible to use to70 to to75 as inverter timer output when inverter timer output is specified by dcen1. the operation mode can be selected as 6 bits 1, or 4 bits 1, by setting byte01. by setting inv1, it is possible to invert the output waveform. also, by setting pwmcl1 and pwmch1, it is possible to perform pwm modulation of the output pattern. if real-time output was disabled (rtpoe01 = 0) when rtpm01n = 1 and inv1 = 0, then to70 to to75 output 0. the relationship between the settings for each bit of the control register and the real-time output is shown in table 10-7, and an example of the operation timing is shown in figure 10-12. remark byte01: bit 5 of real-time output port control register 1 (rtpc01) dcen1: bit 7 of dc control register 1 (dcctl1) inv1: bit 4 of dc control register 1 (dcctl1) pwmcl1, pwmch1: bits 5 and 6 of dc control register 1 (dcctl1) rtpm01n: bit n (n = 0 to 5) of real-time output port mode register 1 (rtpm01) chapter 10 real-time output port 197 user? manual u13029ej7v1ud table 10-7. relationship between settings of each bit of control register and real-time output ce7 dcen1 inv1 pwmch1/ rtpoe01 rtpm01n rtbh01m/ pin to7n status pwmcl1 rtbl01m 0 hi-z 10 to7n 1000 ?ow?output 10 ?ow?output 10 ?ow?output 1 ?igh?output 10 to7n 10 to7n 10 to7n 1 ?igh?output 100 ?igh?output 10 ?igh?output 10 ?igh?output 1 ?ow?output 10 to7n 10 to7n 10 to7n 1 ?ow?output ce7: bit 7 of inverter timer control register 7 (tmc7) dcen1: bit 7 of dc control register (dcctl1) inv1: bit 4 of dcctl1 pwmch1: bit 6 of dcctl1 pwmcl1: bit 5 of dcctl1 rtpoe01: bit 7 of real-time output port control register 1 (rtpc01) rtpm01n: bit n of real-time output port mode register 1 (rtpm01) rtbh01m: bit m of real-time output buffer register 1h (rtbh01) rtbl01m: bit m of real-time output buffer register 1l (rtbl01) n = 0 to 5 m = 0 to 3 : don? care chapter 10 real-time output port user? manual u13029ej7v1ud 198 figure 10-12. real-time output port operation timing example (6 bits 1) (1/3) (a) 6 bits 1 channel, inverted output disabled, no pwm modulation (byte01 = 1, inv1 = 0, pwmch1 = 0, pwmcl1 = 0) a: inttm001 software processing (rtbh01, rtbl01 write) a 01h 02h 03h 04h 05h 06h 07h 08h 09h 01h l l 02h 03h 04h 05h 06h 07h 08h 09h 0ah aaaaaaaaa inttm001 cpu operation rtbh01, rtbl01 output latch to70 output latch to71 output latch to72 output latch to73 output latch to74 output latch to75 output latch to70 to to75 chapter 10 real-time output port 199 user? manual u13029ej7v1ud figure 10-12. real-time output port operation timing example (6 bits 1) (2/3) (b) 6 bits 1 channel, inverted output enabled, no pwm modulation (byte01 = 1, inv1 = 1, pwmch1 = 0, pwmcl1 = 0) a: inttm001 software processing (rtbh01, rtbl01 write) a 01h 02h 03h 04h 05h 06h 07h 08h 09h 01h h h 02h 03h 04h 05h 06h 07h 08h 09h 0ah aaaaaaaaa inttm001 cpu operation rtbh01, rtbl01 output latch to70 output latch to71 output latch to72 output latch to73 output latch to74 output latch to75 output latch to70 to to75 chapter 10 real-time output port user? manual u13029ej7v1ud 200 figure 10-12. real-time output port operation timing example (6 bits 1) (3/3) (c) 6 bits 1 channel, inverted output enabled, pwm modulation (byte01 = 1, inv1 = 1, pwmch1 = 1, pwmcl1 = 1) a: inttm001 software processing (rtbh01, rtbl01 write) a 01h 02h 03h 04h 05h 06h 07h 08h 09h 01h h h 02h 03h 04h 05h 06h 07h 08h 09h 0ah aaaaaaaaa inttm001 cpu operation rtbh01, rtbl01 output latch to70 output latch to71 output latch to72 output latch to73 output latch to74 output latch to75 output latch to70 to to75 chapter 10 real-time output port 201 user? manual u13029ej7v1ud 10.5 using real-time output port when using the real-time output port, perform the following steps. (1) disable real-time output operation. clear bit 7 (rtpoe0n) of real-time output port control register n (rtpc0n) to 0. (2) initial setting set the initial value to the port output latch (real-time output port 0 only). specify the real-time output port mode in 1-bit units. set real-time output port mode register n (rtpm0n). select the operation mode (trigger and a valid edge). set bits 4, 5, and 6 (extr00, byte00, and rtpeg00) of rtpc00 or set bit 5 (byte01) of rtpc01. for real-time output port 0, set an initial value equal to the port output latch in real-time output buffer register 0 (rtbh00, rtbl00). for real-time output port 1, set an initial value in real-time output buffer register 1 (rtbh01, rtbl01). set dc control register n (dcctln). (3) enable the real-time output operation. rtpoe0n = 1 (4) set the port output latch to 0 (only for real-time output port 0). remark for real-time output port 0, the value output by the real-time output operation is the ored value of the output latch of the port and real-time output (see figure 10-1 (a) ). therefore, when real- time output port 0 is used, the port output latch should be set to 0 after the real-time output operation is enabled (rtpoe00 = 0 1) until the first transfer trigger is generated. (5) set the next output to rtbh0n and rtbl0n before the selected transfer trigger is generated. (6) sequentially set the next real-time output value to rtbh0n and rtbl0n by using the interrupt servicing corresponding to the selected trigger. remark n = 0, 1 10.6 notes on real-time output port (1) before performing the initial setting, disable the real-time output operation by clearing bit 7 (rtpoe0n) of real- time output port control register n (rtpc0n) to 0 (n = 0, 1). (2) once the real-time output operation has been disabled (rtpoe0n = 0), be sure to set the same initial value as the output latch to real-time output buffer register n (rtbh0n and rtbl0n) before enabling the real-time output operation (rtpoe0n = 0 1) (n = 0, 1). user? manual u13029ej7v1ud 202 chapter 11 a/d converter 11.1 function of a/d converter the a/d converter converts analog input signals into digital values, and consists of eight channels (ani0 to ani7) with a resolution of 10 bits. this a/d converter is of successive approximation type, and the result of conversion is held by 10-bit a/d conversion result register 0 (adcr0). a/d conversion can be started in the following two ways. (1) hardware start conversion is started by trigger input (adtrg; rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting a/d converter mode register 0 (adm0). one analog input channel is selected from ani0 to ani7 and a/d conversion is executed. a/d conversion is stopped, if it was started by means of hardware, after the conversion is complete, and an interrupt request (intad0) is generated. when a/d conversion is started by software, conversion is repeatedly performed. each time conversion is completed once, intad0 is generated. 11.2 configuration of a/d converter the a/d converter includes the following hardware. table 11-1. configuration of a/d converter item configuration analog input 8 channels (ani0 to ani7) control registers a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) registers successive approximation register (sar) a/d conversion result register 0 (adcr0) chapter 11 a/d converter 203 user? manual u13029ej7v1ud figure 11-1. a/d converter block diagram note specify the valid edge by using bit 3 (egp3, egn3) of the external interrupt rising/falling edge enable registers (egp, egn) (refer to figure 14-5 format of external interrupt rising edge enable register and external interrupt falling edge enable register ). ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 selector note analog input channel specification register 0 (ads0) trigger enable sample & hold circuit adcs0 internal bus edge detector controller av dd voltage comparator tap selector intad0 intp3 successive approximation register (sar) adtrg/intp3/p03 trg0 fr02 fr01 fr00 ega01 ega00 a/d conversion result register 0 (adcr0) av ref av ss 0 3 ads02 ads01 ads00 a/d converter mode register 0 (adm0) av ss edge detector chapter 11 a/d converter user? manual u13029ej7v1ud 204 (1) successive approximation register (sar) this register compares the voltage value of an analog input with the value of a voltage tap (compare voltage) from the series resistor string, and holds the result of the comparison starting from the most significant bit (msb). when the result is held down to the least significant bit (lsb) (end of a/d conversion), the contents of sar are transferred to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) this is a 16-bit register that stores the results of a/d conversion. the lower 6 bits are fixed to 0. every time an a/d conversion is complete, the conversion results are loaded from the successive approximation register (sar). the loaded data is stored in adcr0 in order from the most significant bit (msb). adcr0 is read with a 16-bit memory manipulation instruction. reset input makes the contents of this register undefined. caution when a write operation is performed on a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0), the contents of adcr0 may become undefined. read the conversion results after the conversion operation is complete and before the write operation to adm0 and ads0. correct conversion results may not read out at a timing other than the above. (3) sample & hold circuit the sample & hold circuit samples analog input signals sequentially sent from the input circuit on a one-by- one basis, and sends the sampled signals to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input with the output voltage of the series resistor string. (5) series resistor string the series resistor string is connected between av ref and av ss and generates the voltage to be compared with the analog input. (6) ani0 to ani7 pins these are the eight analog input pin channels of the a/d converter. they input the analog signals that are converted to digital values. symbol adcr0 address after reset r/w ff18h, ff19h undefined r ff19h ff18h 0 0 0 0 0 0 chapter 11 a/d converter 205 user? manual u13029ej7v1ud cautions 1. observe the rated input voltage range of ani0 to ani7. if a voltage of av ref or higher, or av ss or lower (even within the range of absolute maximum ratings) is applied to a channel, the converted value of that channel becomes undefined, or the converted value of the other channels may be affected. 2. the analog input pins (ani0 to ani7) are also used as input port pins (p10 to p17). when a/d conversion is performed with any of ani0 to ani7 selected, do not execute the input instruction to port 1 while conversion is in progress; otherwise, the conversion resolution may be degraded. if a digital pulse is applied to the pins adjacent to the pin currently being used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, do not apply a pulse to the adjacent pins to the pin under going a/d conversion. (7) avref pin this pin inputs a reference voltage to the a/d converter. based on the voltage applied between av ref and av ss , the signal input to ani0 to ani7 is converted into a digital signal. caution a series resistor string of several 10 k ? is connected between the av ref and av ss pins. if the output impedance of the reference voltage source is high, therefore, the error of the reference voltage increases by connecting the impedance in series with the series resistor string between the av ref and av ss pins. (8) av ss pin this is the ground pin of the a/d converter. always make this pin the same potential as the v ss0 pin even when the a/d converter is not used. (9) av dd pin this is the analog power supply pin of the a/d converter. always make this pin the same potential as the v dd0 pin even when the a/d converter is not used. 11.3 registers controlling a/d converter the following two registers control the a/d converter. a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) (1) a/d converter mode register 0 (adm0) this register sets conversion time of an analog input to be converted into a digital value, starts/stops the conversion operation, and sets an external trigger. adm0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. chapter 11 a/d converter user? manual u13029ej7v1ud 206 figure 11-2. format of a/d converter mode register 0 notes 1. set the a/d conversion time so that it satisfies the following ratings. chapter 11 a/d converter 207 user? manual u13029ej7v1ud (2) analog input channel specification register 0 (ads0) this register sets the input port of the analog voltage to be converted into a digital value. ads0 is set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 11-3. format of analog input channel specification register 0 6543210 7 symbol ads0 0 0 0 0 0 ads02 ads01 ads00 analog input channel specification ani0 ani1 ani3 ani4 ani6 ani2 ani5 ani7 ff81h 00h r/w address after reset r/w 0 0 0 0 1 1 1 1 ads02 0 0 1 1 0 0 1 1 ads01 0 1 1 0 0 1 0 1 ads00 chapter 11 a/d converter user? manual u13029ej7v1ud 208 11.4 operation of a/d converter 11.4.1 basic operation of a/d converter <1> select one channel for a/d conversion using analog input channel specification register 0 (ads0). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when the voltage has been sampled for a specific time, the sample & hold circuit enters the hold status, and holds the input analog voltage until a/d conversion is completed. <4> bit 9 of the successive approximation register (sar) is set. the voltage tap of the series resistor string is set to (1/2) av ref by the tap selector. <5> the voltage differential between the voltage tap of the series resistor string and the analog input is compared by the voltage comparator. if the analog input is higher than (1/2) av ref , the msb of the sar remains set. if it is less than (1/2) av ref , the msb is reset. <6> next, bit 8 of the sar is automatically set, and the next voltage differential is compared. here the voltage tap of the series resistor string is selected as follows, according to the value of bit 9 to which the result of the first comparison has already been set. bit 9 = 1: (3/4) av ref bit 9 = 0: (1/4) av ref this voltage tap and analog input voltage are compared, and bit 8 of the sar is manipulated as follows, according to the result of the comparison. analog input voltage voltage tap: bit 8 = 1 analog input voltage < voltage tap: bit 8 = 0 <7> in this way, all the bits of the sar, including bit 0, are compared. <8> when all the 10 bits of the sar have been compared, the sar holds the valid digital results, which are then transferred and latched to a/d conversion result register 0 (adcr0). at the same time, an a/d conversion end interrupt request (intad0) can be generated. caution the first a/d conversion value immediately after starting the a/d conversion operation may not satisfy ratings. chapter 11 a/d converter 209 user? manual u13029ej7v1ud figure 11-4. basic operation of a/d converter a/d conversion is performed continuously, until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset to 0 by software. if the data of adm0 or analog input channel specification register 0 (ads0) is rewritten during a/d conversion, the conversion is initialized. if the adcs0 bit is set to 1 at this time, conversion is performed again from the start. reset input makes the contents of a/d conversion result register 0 (adcr0) undefined. operation of a/d converter sar adcr0 intad0 un- defined conversion result conversion result sampling sampling time a/d conversion conversion time chapter 11 a/d converter user? manual u13029ej7v1ud 210 11.4.2 input voltage and conversion result the relationship between the analog voltage input to the analog input pins (ani0 to ani7) and a/d conversion result (value stored in a/d conversion result register 0 (adcr0)) is as follows. adcr0 = int ( 1,024 + 0.5) or, (adcr0 ?0.5) v in < (adcr0 + 0.5) remark int( ): function returning integer of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr0: value of a/d conversion result register 0 (adcr0) figure 11-5 shows the relationship between the analog input voltage and a/d conversion result. figure 11-5. relationship between analog input voltage and a/d conversion result v in av ref av ref 1,024 av ref 1,024 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 0 1 2 3 1,021 1,022 1,023 a/d conversion result (adcr0) input voltage/av ref chapter 11 a/d converter 211 user? manual u13029ej7v1ud 11.4.3 operation mode of a/d converter one analog input channel is selected from ani0 to ani7 for a/d conversion using analog input channel specification register 0 (ads0). a/d conversion can be started in the following two ways. hardware start: conversion is started by trigger input (adtrg; rising edge/falling edge, or both rising and falling edges can be specified). software start: conversion is started by setting a/d converter mode register 0 (adm0). the result of the a/d conversion is stored in a/d conversion result register 0 (adcr0), and at the same time, an interrupt request signal (intad0) is generated. (1) a/d conversion operation by hardware start the a/d conversion operation is in standby when both bits 6 (trg0) and 7 (adcs0) of a/d converter mode register 0 (adm0) are set to 1. when an external trigger signal (adtrg) is input, the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0) is converted into a digital value. when a/d conversion is complete, the result of the conversion is stored in a/d conversion result register 0 (adcr0), and an interrupt request signal (intad0) is generated. once a/d conversion is started and when one a/d conversion is complete, the next a/d conversion is not started unless a new external trigger signal is input. if ads0 is rewritten during a/d conversion, the ad conversion under execution is stopped, and stands by until a new external trigger signal is input. when the external trigger signal is input, a/d conversion is performed again from the start. if ads0 is rewritten while the a/d converter is standing by, the new a/d conversion operation will be started when the next external trigger signal is input. when 0 is written to the adcs0 bit of adm0 during a/d conversion, the conversion is immediately stopped. caution when p03/intp3/adtrg is used as an external trigger input (adtrg), specify the valid edge by using bits 1 and 2 (ega00 and ega01) of a/d converter mode register 0 (adm0) and set the interrupt mask flag (pmk3) to 1. figure 11-6. a/d conversion by hardware start (with falling edge specified) remark n = 0, 1, ..., 7 m = 0, 1, ..., 7 anin intad0 adcr0 a/d conversion adtrg standby status anin anin standby status anin standby status anim anim anin anin anim anim setting adm0 adcs0 = 1, trg0 = 1 rewriting ads0 anim chapter 11 a/d converter user? manual u13029ej7v1ud 212 (2) a/d conversion by software start by setting bit 6 (trg0) of a/d converter mode register 0 (adm0) to 0 and setting bit 7 (adcs0) to 1, the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0) is converted into a digital value. when a/d conversion is complete, the result of the conversion is stored in a/d conversion result register 0 (adcr0), and an interrupt request signal (intad0) is generated. when a/d conversion is started once, and one a/d conversion is complete, the next a/d conversion is immediately started. in this way, a/d conversion is repeatedly executed until new data is written to ads0. if ads0 is rewritten during a/d conversion, the conversion under execution is stopped, and a/d conversion of the newly selected analog input channel is started. if data whose adcs0 is 0 is written to adm0 during a/d conversion, the conversion is immediately stopped. figure 11-7. a/d conversion by software start remark n = 0, 1, ..., 7 m = 0, 1, ..., 7 anin intad0 adcr0 a/d conversion anin anin anim anim anin anim setting adm0 adcs0 = 1, trg0 = 0 rewriting ads0 adcs0 = 0 stopped anin conversion is stopped. conversion result is not retained. chapter 11 a/d converter 213 user? manual u13029ej7v1ud 11.5 notes on a/d converter (1) current consumption in standby mode the a/d converter stops operating in the standby mode. at this time, the current consumption can be reduced by stopping the conversion operation (by clearing bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0). an example of reducing the current consumption in standby mode is shown in figure 11-8. figure 11-8. example of reducing current consumption in standby mode (2) ani0 to ani7 input range observe the rated range of the ani0 to ani7 input voltage. if a voltage of av ref or higher, or av ss or lower (even within the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflict <1> conflict between writing a/d conversion result register 0 (adcr0) on completion of conversion and reading adcr0 by instruction reading adcr0 has priority. after it has been read, a new conversion result is written to adcr0. <2> conflict between writing adcr0 on completion of conversion and external trigger signal input the external trigger signal is not acknowledged during a/d conversion. therefore, the external trigger signal is not acknowledged while adcr0 is being written. <3> conflict between writing adcr0 on completion of conversion and writing a/d converter mode register 0 (adm0) or writing analog input channel specification register 0 (ads0) writing adm0 or ads0 has priority. adcr0 is not written. the conversion end interrupt request signal (intad0) is not generated. series resistor string adcs0 p-ch av ref av ss chapter 11 a/d converter user? manual u13029ej7v1ud 214 (4) countermeasures against noise to keep the resolution of 10 bits, noise superimposed on the av ref and ani0 to ani7 pins must be suppressed as much as possible. the higher the output impedance of the analog input source, the greater the effect. to suppress noise, connecting an external capacitor as shown in figure 11-9 is recommended. figure 11-9. processing analog input pin (5) ani0/p10 to ani7/p17 the analog input pins (ani0 to ani7) are also used as input port pins (p10 to p17). when a/d conversion is performed with any of ani0 to ani7 selected, do not execute the input instruction to port 1 while conversion is in progress; otherwise, the conversion resolution may be degraded. if a digital pulse is applied to the pins adjacent to the pin currently being used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, do not apply a pulse to the pins adjacent to the pin under going a/d conversion. (6) input impedance of ani0 to ani7 pins this a/d converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. therefore at times other than sampling, only the leak current is output. during sampling, the current for charging the capacitor is also output, so the input impedance fluctuates and has no meaning. however, to ensure adequate sampling, it is recommended that the output impedance of the analog input source be set to below 10 k ? , or a 100 pf capacitor be connected to the ani0 to ani7 pins (see figure 11- 9 ). (7) input impedance to av ref pin a series resistor string of several 10 k ? is connected between the av ref and av ss pins. if the output impedance of the reference voltage source is high, therefore, the reference voltage error increases when connecting the impedance in series with the series resistor string between the av ref and av ss pins. reference voltage input av ref ani0 to ani7 v dd0 av dd av ss v ss0 c = 100 to 1000 pf if there is a possibility that noise of av ref or higher, or av or lower is input, ss clamp the noise by using a diode with a low v f (0.3 v max.). av ref chapter 11 a/d converter 215 user? manual u13029ej7v1ud (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even when the contents of analog input channel specification register 0 (ads0) are changed. when the analog input pin is changed during a/d conversion, therefore, the chances are that the a/d conversion result of the old analog input and interrupt request flags was set immediately before the contents of ads0 was rewritten. consequently, adif may be set even if a/d conversion for the newly specified analog input pin has not yet been completed when adif is read immediately after ads0 has been rewritten (refer to figure 11-10 ). to resume a/d conversion once it has been stopped, clear adif first. figure 11-10. a/d conversion end interrupt request generation timing remark n = 0, 1, ......, 7 n = 0, 1, ......, 7 (9) av dd pin the av dd pin is the power supply pin to the analog circuit and supplies power to the input circuit of ani0/p10 to ani7/p17. therefore, even in applications that can be switched over to a backup power source, be sure to apply the same voltage as v dd0 as shown in figure 11-11. figure 11-11. processing of av dd pin a/d conversion adcr0 intad0 rewriting adm0 (anln conversion starts) rewriting ads0 (anlm conversion starts) adif is set, but conversion of anlm is not complete anin anin anim anim anin anin anim anim av ref v dd0 av dd v ss0 av ss main power supply backup capacitor chapter 11 a/d converter user? manual u13029ej7v1ud 216 (10) conversion result immediately after start of a/d conversion the first a/d conversion value immediately after starting the a/d conversion operation may not satisfy the ratings. poll the a/d conversion end interrupt request (intad0) and discard the first conversion result. (11) reading a/d conversion result register 0 (adcr0) when performing a write operation to a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0), the contents of adcr0 may become undefined. read the conversion results after the conversion operation is complete and before the write operation to adm0 and ads0. correct conversion results may not be read out at a timing other than the above. (12) timing at which a/d conversion result is undefined the a/d conversion value may be undefined if the timing of completion of a/d conversion and the timing of stopping the a/d conversion conflict. therefore, read the a/d conversion result during the a/d conversion operation. to read the conversion result after stopping the a/d conversion operation, be sure to stop the a/ d conversion before the next conversion ends. figures 11-12 and 11-13 show the timing of reading the conversion result. figure 11-12. timing of reading conversion result (when conversion result is undefined) figure 11-13. timing of reading conversion result (when conversion result is normal) normal conversion result undefined value a/d conversion complete a/d conversion complete normal conversion result is read a/d conversion is stopped undefined value is read adcr0 intad0 adcs0 normal conversion result a/d conversion complete normal conversion result is read a/d conversion is stopped adcr0 intad0 adcs0 chapter 11 a/d converter 217 user? manual u13029ej7v1ud (13) notes on board design locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may be affected by the noise of the digital circuits. in particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. otherwise, the a/d conversion characteristics may be affected by the noise of the digital line. connect av ss0 and v ss0 at one location on the board where the voltages are stable. (14) av ref pin connect a capacitor to the av ref pin to minimize conversion errors due to noise. if an a/d conversion operation has been stopped and is then started, the voltage applied to the av ref pin becomes unstable, causing the accuracy of the a/d conversion to drop. to prevent this, also connect a capacitor to the av ref pin. figure 11-14 shows an example of connecting a capacitor. figure 11-14. example of connecting capacitor to av ref pin remark c1: 4.7 f to 10 f (reference value) c2: 0.01 f to 0.1 f (reference value) connect c2 as close to the pin as possible. (15) internal equivalent circuit of ani0 to ani7 pins and permissible signal source impedance to complete sampling within the sampling time with sufficient a/d conversion accuracy, the impedance of the sensor or other signal source must be sufficiently low. figure 11-15 shows the internal equivalent circuit of the ani0 to ani7 pins. if the impedance of the signal source is high, connect capacitors with a high capacitance to pins ani0 to ani7. an example of this is shown in figure 11-16. in this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created. to convert a high-speed analog signal or to convert an analog signal in the scan mode, insert a low-impedance buffer. av ref av ss c 2 c 1 chapter 11 a/d converter user? manual u13029ej7v1ud 218 figure 11-15. internal equivalent circuit of pins ani0 to ani7 remark n = 0 to 7 table 11-2. resistances and capacitances of equivalent circuit (reference values) av ref r1 r2 c1 c2 c3 2.7 v 12 k ? 8 k ? 8 pf 3 pf 2 pf 4.5 v 4 k ? 2.7 k ? 8 pf 1.4 pf 2 pf caution the resistances and capacitances in table 11-2 are not guaranteed values. figure 11-16. example of connection if signal source impedance is high remark n = 0 to 7 c3 c2 r2 r1 chapter 11 a/d converter 219 user? manual u13029ej7v1ud 11.6 how to read a/d converter characteristics tables this section describes the technical terms peculiar to the a/d converter. (1) resolution this is the minimum identifiable analog input voltage. the ratio of 1 digital output bit to an analog input voltage is said to be 1 lsb (least significant bit). the ratio of the full scale to 1 lsb is expressed in %fsr (full scale range). where the resolution is 10 bits, 1 lsb = 1/2 10 = 1/1024 = 0.098% fsr the accuracy does not depend on the resolution and is determined by the overall error. (2) overall error this is the maximum difference between actually measured and theoretical values. the overall error indicates a zero-scale error and full-scale error, an integral linearity error, differential linearity error, and a combination of these errors. note that the overall error specified in the characteristics table does not include the quantization error. (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. since the a/d converter converts an analog input voltage in the range of 1/2 lsb into the same digital code, a quantization error is unavoidable. this error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error specified in the characteristics table. chapter 11 a/d converter user? manual u13029ej7v1ud 220 figure 11-17. overall error figure 11-18. quantization error (4) zero-scale error this is the difference between the actually measured value and the theoretical value (1/2 lsb) of an analog input voltage when the digital output changes from 0...000 to 0...001. if the measured value is greater than the theoretical value, it is the difference between the actually measured value and the theoretical value (3/ 2 lsb) of the analog input voltage when the digital output changes from 0...001 to 0...010. (5) full-scale error this is the difference between the actually measured value and the theoretical value (full scale -3/2 lsb) of an analog input voltage when the digital output changes from 1...110 to 1...111. (6) integral linearity error this is the degree to which the conversion characteristics shift from the ideal straight line. it indicates the maximum difference between the measured value and the ideal straight line where the zero-scale error and full-scale error are 0. (7) differential linearity error this is the difference between the actually measured value and the theoretical value of an input voltage when the conversion result changes from a certain value by 1. the differential linearity error indicates the degree of dispersion (relative drift) of input voltage variation required when changing from each conversion value in comparison to the integral linearity error that indicates the absolute value of the drift from the theoretical value. quantization error 1 ...... 1 0 ...... 0 0av ref analog input digital output 1/2lsb 1/2lsb ideal straight line overall error 1 ...... 1 0 ...... 0 0av ref analog input digital output chapter 11 a/d converter 221 user? manual u13029ej7v1ud figure 11-19. zero-scale error figure 11-20. full-scale error figure 11-21. integral linearity error figure 11-22. differential linearity error (8) conversion time time required from when an analog input voltage is given until the digital output is obtained. sampling time is included in the conversion time in the characteristics table. (9) sampling time time during which an analog switch is on to load an analog voltage to the sample & hold circuit. sampling time conversion time 111 011 010 001 000 0123 av ref zero-scale error ideal straight line analog input (lsb) digital output (lower 3 bits) 1 ...... 1 0 ...... 0 0av ref analog input digital output ideal straight line integral linearity error analog input ideal width of 1lsb digital output differential linearity 1 ...... 1 0 ...... 0 av ref 111 110 101 000 0 ref? ref? ref? vv vav ref full-scale error ideal straight line analog input (lsb) digital output (lower 3 bits) user? manual u13029ej7v1ud 222 chapter 12 serial interfaces uart00 and uart01 12.1 function of serial interfaces serial interfaces uart00 and uart01 have the following three modes. operation stop mode asynchronous serial interface (uart) mode infrared data transfer mode (uart00 only) (1) operation stop mode this mode is used when serial transfer is not carried out, and is to reduce power consumption. (2) asynchronous serial interface (uart) mode in this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. a dedicated uart baud rate generator is incorporated, allowing communication over a wide range of baud rates. programming baud rate generator control registers 0 and 1 (brgc00 and brgc01) allows a baud rate selection of 600 bps to 115.2 kbps (@ f x = 8.38 mhz operation) or 1200 bps to 153.6 kbps (@ f x = 12 mhz operation) for uart00 and 300 bps to 38.4 kbps (@ f x = 8.38 mhz operation) or 600 bps to 76.8 kbps (@ f x = 12 mhz operation) for uart01. (3) infrared data transfer mode (uart00 only) this mode allows communication at a baud rate of 115.2 kbps (@ f x = 7.3728 mhz operation). chapter 12 serial interfaces uart00 and uart01 223 user? manual u13029ej7v1ud 12.2 configuration of serial interfaces serial interfaces uart00 and uart01 includes the following hardware. table 12-1. configuration of serial interfaces item configuration registers transmit shift register n (txs0n) receive shift register n (rx0n) receive buffer register n (rxb0n) control registers asynchronous serial interface mode register n (asim0n) asynchronous serial interface status register n (asis0n) baud rate generator control register n (brgc0n) port mode register 2 (pm2) note note refer to figure 4-4 block diagram of p20 to p26 . remark n = 0, 1 figure 12-1. block diagram of serial interface uart00 note refer to figure 12-2 for the baud rate generator configuration. internal bus receive buffer register 0 (rxb00) rxd00/p20 txd00/p21 receive shift register 0 (rx00) pe00 fe00 ove00 asynchronous serial interface status register 0 ( asis00) intser0 intst0 baud rate generator note f x /2 to f x /2 8 txe00 rxe00 ps001 ps000 cl00 sl00 isrm00 irdam00 asynchronous serial interface mode register 0 ( asim00) intsr0 receive controller (parity check) transmit shift register 0 (txs00) transmit controller (parity addition) chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 224 figure 12-2. block diagram of uart00 baud rate generator 5-bit counter 5-bit counter decoder match match start bit sampling clock selector 1/2 1/2 f x /2 to f x /2 8 34 baud rate generator control register 0 (brgc00) rxe00 txe00 reception clock transmission clock start bit detection internal bus tps002 tps001 tps000 mdl003 mdl002 mdl001 mdl000 remark txe00: bit 7 of asynchronous serial interface mode register 0 (asim00) rxe00: bit 6 of asynchronous serial interface mode register 0 (asim00) chapter 12 serial interfaces uart00 and uart01 225 user? manual u13029ej7v1ud figure 12-3. block diagram of serial interface uart01 5-bit counter 5-bit counter decoder match match start bit sampling clock selector 1/2 1/2 f x /2 2 to f x /2 9 34 baud rate generator control register 1 (brgc01) rxe01 txe01 reception clock transmission clock start bit detection internal bus tps012 tps011 tps010 mdl013 mdl012 mdl011 mdl010 note refer to figure 12-4 for the baud rate generator configuration. figure 12-4. block diagram of uart01 baud rate generator remark txe01: bit 7 of asynchronous serial interface mode register 1 (asim01) rxe01: bit 6 of asynchronous serial interface mode register 1 (asim01) internal bus receive buffer register 1 (rxb01) rxd01/p22 txd01/p23 receive shift register 1 (rx01) pe01 fe01 ove01 asynchronous serial interface status register 1 ( asis01) intst1 baud rate generator note f x /2 2 to f x /2 9 txe01 rxe01 ps011 ps010 cl01 sl01 0 0 asynchronous serial interface mode register 1 ( asim01) intsr1 receive controller (parity check) transmit shift register 1 (txs01) transmit controller (parity addition) chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 226 (1) transmit shift register n (txs0n) this register is used to set the transmit data. the data written in txs0n is transmitted as serial data. if the data length is specified as 7 bits, bits 0 to 6 of the data written in txs0n are transferred as transmit data. writing data to txs0n starts the transmit operation. txs0n is written to with an 8-bit memory manipulation instruction. it cannot be read. reset input sets txs0n to ffh. caution txs0n must not be written to during a transmit operation. txs0n and receive buffer register n (rxb0n) are allocated to the same address, and when a read is performed, the value of rxb0n is read. (2) receive shift register n (rx0n) this register is used to convert serial data input to the rxd0n pin to parallel data. when one byte of data is received, the receive data is transferred to receive buffer register n (rxb0n). rx0n cannot be directly manipulated by a program. (3) receive buffer register n (rxb0n) this register holds receive data. each time one byte of data is received, new receive data is transferred from receive shift register n (rx0n). if the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of rxb0n, and the msb of rxb0n is always set to 0. rxb0n is read with an 8-bit memory manipulation instruction. it cannot be written to. reset input sets rxb0n to ffh. caution rxb0n and transmit shift register n (txs0n) are allocated to the same address, and when a write is performed, the value is written to txs0n. (4) transmission control circuit this circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data written in transmit shift register n (txs0n) in accordance with the contents set in asynchronous serial interface mode register n (asim0n). (5) reception control circuit this circuit controls receive operations in accordance with the contents set in asynchronous serial interface mode register n (asim0n). it performs error checks for parity errors, etc., during a receive operation, and if an error is detected, sets a value in asynchronous serial interface status register n (asis0n) in accordance with the error contents. remark n = 0, 1 chapter 12 serial interfaces uart00 and uart01 227 user? manual u13029ej7v1ud 12.3 registers controlling serial interfaces the following six registers control the serial interfaces uart00 and uart01. asynchronous serial interface mode registers 0, 1 (asim00, asim01) asynchronous serial interface status registers 0, 1 (asis00, asis01) baud rate generator control registers 0, 1 (brgc00, brgc01) (1) asynchronous serial interface mode registers 0, 1 (asim00, asim01) asim00 and asim01 are 8-bit registers that control the serial transfer operation of the asynchronous serial interface. these registers are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. caution set the port mode register (pm2x) in the uart mode, as shown below. set each output latch to 0. for reception set p20 (rxd00) and p22 (rxd01) to input mode (pm20 = 1, pm22 = 1) for transmission set p21 (txd00) and p23 (txd01) to output mode (pm21 = 0, pm23 = 0) for transmission and reception set p20 and p22 to input mode and p21 and p23 to output mode. chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 228 figure 12-5. format of asynchronous serial interface mode register 0 notes 1. the uart or infrared data transfer mode is specified by txe00 and rxe00. 2. when using the infrared data transfer mode, be sure to clear baud rate generator control register 0 (brgc00) to 00h. caution before changing the operation mode, be sure to stop the serial transmission/reception. 6543210 7 symbol asim00 txe00 rxe00 ps001 ps000 cl00 sl00 isrm00 irdam00 ffa0h 00h r/w address after reset r/w 0 0 operation stopped uart mode (reception only) uart mode (transmission only) uart mode (transmission/reception) 1 1 0 1 0 1 txe00 operation mode rxe00 character length specification cl00 0 1 7 bits 8 bits transmit data stop bit length specification sl00 0 1 1 bit 2 bits 0 no parity odd parity 0 transmission = always 0 parity addition reception = parity not checked (parity error not generated) 1 even parity 1 0 1 0 1 ps001 parity bit specification ps000 reception end interrupt control on occurrence of error isrm00 0 1 reception end interrupt request generated on occurrence of error. reception end interrupt request not generated on occurrence of error. infrared data transfer mode operation specification note 1 irdam00 0 1 uart (transmission/reception) mode infrared data transfer (transmission/reception) mode note 2 function of rxd00/p20 pin function of txd00/p21 pin port function (p20) serial function (rxd00) port function (p20) serial function (rxd00) port function (p21) serial function (txd00) chapter 12 serial interfaces uart00 and uart01 229 user? manual u13029ej7v1ud figure 12-6. format of asynchronous serial interface mode register 1 caution before changing the operation mode, be sure to stop the serial transmission/reception. 6543210 7 symbol asim01 txe01 rxe01 ps011 ps010 cl01 sl01 0 0 ffa8h 00h r/w address after reset r/w 0 0 operation stopped uart mode (reception only) uart mode (transmission only) uart mode (transmission/reception) 1 1 0 1 0 1 txe01 operation mode rxe01 character length specification cl01 0 1 7 bits 8 bits transmit data stop bit length specification sl01 0 1 1 bit 2 bits 0n o parity odd parity 0 transmission = always 0 parity addition reception = parity not checked (parity error not generated) 1 even parity 1 0 1 0 1 ps011 parity bit specification ps010 function of rxd01/p22 pin function of txd01/p23 pin port function (p22) serial function (rxd01) port function (p22) serial function (rxd01) port function (p23) serial function (txd01) chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 230 (2) asynchronous serial interface status registers 0, 1 (asis00, asis01) asis00 and asis01 are the registers that indicate the error contents when a receive error occurs. these registers can be read with an 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 12-7. format of asynchronous serial interface status register 0 notes 1. even if the stop bit length is set to 2 bits using bit 2 (sl00) of asynchronous serial interface mode register 0 (asim00), only 1 stop bit is detected during reception. 2. if an overrun error occurs, be sure to read receive buffer register 0 (rxb00). until rxb00 is read, an overrun error persistently occurs each time data is received. 6543210 7 symbol asis00 0 0 0 0 0 pe00 fe00 ove00 ffa1h 00h r address after reset r/w parity error flag pe00 0 1 parity error does not occur. parity error occurs (transmit data parity specification and receive data parity do not match). framing error flag fe00 0 1 framing error does not occur. framing error occurs note 1 (stop bit not detected). overrun error flag ove00 0 1 overrun error does not occur. overrun error occurs note 2 (next receive completed before data is read from receive buffer register). chapter 12 serial interfaces uart00 and uart01 231 user? manual u13029ej7v1ud figure 12-8. format of asynchronous serial interface status register 1 notes 1. even if the stop bit length is set to 2 bits using bit 2 (sl01) of asynchronous serial interface mode register 1 (asim01), only 1 stop bit is detected during reception. 2. if an overrun error occurs, be sure to read receive buffer register 1 (rxb01). until rxb01 is read, an overrun error persistently occurs each time data is received. (3) baud rate generator control registers 0, 1 (brgc00, brgc01) brgc00 and brgc01 are the registers that set the serial clock of the asynchronous serial interface. these registers are set by an 8-bit memory manipulation instruction. reset input clears these registers to 00h. 6543210 7 symbol asis01 0 0 0 0 0 pe01 fe01 ove01 ffa9h 00h r address after reset r/w parity error flag pe01 0 1 parity error does not occur. parity error occurs (transmit data parity specification and receive data parity do not match). framing error flag fe01 0 1 framing error does not occur. framing error occurs note 1 (stop bit not detected). overrun error flag ove01 0 1 overrun error does not occur. overrun error occurs note 2 (next receive completed before data is read from receive buffer register). chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 232 figure 12-9. format of baud rate generator control register 0 note expanded-specification products only. cautions 1. if a write to brgc00 is performed during communication, the output of the baud rate generator may be disrupted, preventing normal communication from continuing. brgc00 should therefore not be written to during communication. 2. set brgc00 to 00h in the infrared data transfer mode. remarks 1. f x : system clock oscillation frequency 2. f sck : 5-bit counter source clock 3. k: value set in bits mdl000 to mdl003 (0 k 14) 6543210 7 symbol brgc00 0 tps002 tps001 tps000 mdl003 mdl002 mdl001 mdl000 ffa2h 00h r/w address after reset r/w 0 0 6 mhz 3 mhz 1.5 mhz 93.7 khz 0 187 khz 1 1 46.8 khz 0 0 1 0 1 0 1 0 1 0 tps002 5-bit counter source clock selection tps001 tps000 375 khz 750 khz 0 1 1 0 1 0 111 0 0 f sck /16 f sck /17 f sck /18 f sck /22 0 f sck /21 0 0 f sck /23 0 0 0 1 1 0 0 1 0 1 mdl003 baud rate generator input clock selection mdl002 mdl001 f sck /20 f sck /19 0 0 0 1 1 0 011 0 1 0 1 0 mdl000 1 0 1 k 0 1 2 5 6 3 4 7 1 1 f sck /24 f sck /25 f sck /26 f sck /30 1 f sck /29 1 1 setting prohibited 0 0 0 1 1 0 0 1 0 1 f sck /28 f sck /27 1 1 0 1 1 0 111 0 1 0 1 0 1 0 1 8 9 10 13 14 11 12 f x /2 f x /2 2 f x /2 3 f x /2 7 f x /2 6 f x /2 8 f x /2 5 f x /2 4 4.19 mhz 2.1 mhz 1.05 mhz 65.5 khz 131 khz 32.7 khz 262 khz 524 khz at f x = 12 mhz note at f x = 8.38 mhz chapter 12 serial interfaces uart00 and uart01 233 user? manual u13029ej7v1ud figure 12-10. format of baud rate generator control register 1 note expanded-specification products only. caution if a write to brgc01 is performed during communication, the output of the baud rate generator may be disrupted, preventing normal communication from continuing. brgc01 should therefore not be written to during communication. remarks 1. f x : system clock oscillation frequency 2. f sck : 5-bit counter source clock 3. k: value set in bits mdl010 to mdl013 (0 k 14) 6543210 7 symbol brgc01 0 tps012 tps011 tps010 mdl013 mdl012 mdl011 mdl010 ffaah 00h r/w address after reset r/w 0 0 f x /2 4 f x /2 5 f x /2 6 0 f x /2 9 1 1 0 0 1 0 1 0 1 0 1 0 tps012 5-bit counter source clock selection tps011 tps010 f x /2 8 f x /2 7 0 1 1 0 1 0 111 0 0 f sck /16 f sck /17 f sck /18 f sck /22 0 f sck /21 0 0 f sck /23 0 0 0 1 1 0 0 1 0 1 mdl013 baud rate generator input clock selection mdl012 mdl011 f sck /20 f sck /19 0 0 0 1 1 0 011 0 1 0 1 0 mdl010 1 0 1 k 0 1 2 5 6 3 4 7 1 1 f sck /24 f sck /25 f sck /26 f sck /30 1 f sck /29 1 1 setting prohibited 0 0 0 1 1 0 0 1 0 1 f sck /28 f sck /27 1 1 0 1 1 0 111 0 1 0 1 0 1 0 1 8 9 10 13 14 11 12 f x /2 2 f x /2 3 524 khz 262 khz 131 khz 16.4 khz 32.7 khz 65.5 khz 2 mhz 1 mhz 750 khz 375 khz 187 khz 23.4 khz 46.8 khz 93.7 khz 3 mhz 1.5 mhz at f x = 8.38 mhz at f x = 12 mhz note chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 234 12.4 operation of serial interfaces the following three operating modes are available for the serial interfaces uart00 and uart01. operation stop mode asynchronous serial interface (uart) mode infrared data transfer mode (uart00 only) 12.4.1 operation stop mode serial transfer is not executed in this mode. consequently, the power consumption can be reduced. in the operation stop mode, the pins can be used as ordinary port pins. (1) register setting the operation stop mode is set using asynchronous serial interface mode registers 0 and 1 (asim00 and asim01). asim00 and asim01 are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. caution before changing the operation mode, be sure to stop the serial transmission/reception. remark n = 0, 1 12.4.2 asynchronous serial interface (uart) mode in this mode, one byte of data is transmitted/received following a start bit, and full-duplex operation is possible. a baud rate generator is incorporated, enabling communication to be performed at any of a wide range of baud rates. programming baud rate generator control registers 0 and 1 (brgc00 and brgc01) allows a baud rate selection of 600 bps to 115.2 kbps (@ f x = 8.38 mhz operation) or 1200 bps to 153.6 kbps (@ f x = 12 mhz operation) for uart00 and 300 bps to 38.4 kbps (@ fx = 8.38 mhz operation) or 600 bps to 76.8 kbps (@ f x = 12 mhz operation) for uart01. (1) register setting the uart mode is set using asynchronous serial interface mode registers 0 and 1 (asim00 and asim01), asynchronous serial interface status registers 0 and 1 (asis00 and asis01), and baud rate generator control registers 0 and 1 (brgc00 and brgc01). 6543210 7 symbol asim0n txe0n rxe0n ps0n1 ps0n0 cl0n sl0n isrm0n irdam0n ffa0h, 00h r/w ffa4h address after reset r/w 0 0 operation stopped uart mode (reception only) uart mode (transmission only) uart mode (transmission/reception) 1 1 0 1 0 1 txe0n operation mode rxe0n function of rxd00/p20, rxd01/p22 pins function of txd00/p21, txd01/p23 pins port function serial function port function serial function port function serial function chapter 12 serial interfaces uart00 and uart01 235 user? manual u13029ej7v1ud (a) asynchronous serial interface mode registers 0, 1 (asim00, asim01) asim00 and asim01 are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. caution set the port mode register (pm2x) in the uart mode, as shown below. set each output latch to 0. for reception set p20 (rxd00) and p22 (rxd01) to input mode (pm20 = 1, pm22 = 1) for transmission set p21 (txd00) and p23 (txd01) to output mode (pm21 = 0, pm23 = 0) for transmission and reception set p20 and p22 to input mode and p21 and p23 to output mode. 6543210 7 symbol asim00 txe00 rxe00 ps001 ps000 cl00 sl00 isrm00 irdam00 ffa0h 00h r/w address after reset r/w 0 0 operation stopped uart mode (reception only) uart mode (transmission only) uart mode (transmission/reception) 1 1 0 1 0 1 txe00 operation mode rxe00 character length specification cl00 0 1 7 bits 8 bits transmit data stop bit length specification sl00 0 1 1 bit 2 bits 0n o parity odd parity 0t ransmission = always 0 parity addition reception = parity not checked (parity error not generated) 1 even parity 1 0 1 0 1 ps001 parity bit specification ps000 reception end interrupt control on occurrence of error isrm00 0 1 reception end interrupt request generated on occurrence of error. reception end interrupt request not generated on occurrence of error. infrared data transfer mode operation specification note 1 irdam00 0 1 uart (transmission/reception) mode infrared data transfer (transmission/reception) mode note 2 function of rxd00/p20 pin function of txd00/p21 pin port function (p20) serial function (rxd00) port function (p20) serial function (rxd00) port function (p21) serial function (txd00) chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 236 caution before changing the operation mode, be sure to stop the serial transmission/reception. notes 1. the uart or infrared data transfer mode is specified by txe00 and rxe00. 2. when using the infrared data transfer mode, be sure to clear baud rate generator control register 0 (brgc00) to 00h. caution before changing the operation mode, be sure to stop the serial transmission/reception. 6543210 7 symbol asim01 txe01 rxe01 ps011 ps010 cl01 sl01 0 0 ffa8h 00h r/w address after reset r/w 0 0 operation stopped uart mode (reception only) uart mode (transmission only) uart mode (transmission/reception) 1 1 0 1 0 1 txe01 operation mode rxe01 character length specification cl01 0 1 7 bits 8 bits transmit data stop bit length specification sl01 0 1 1 bit 2 bits 0 no parity odd parity 0 transmission = always 0 parity addition reception = parity not checked (parity error not generated) 1 even parity 1 0 1 0 1 ps011 parity bit specification ps010 function of rxd01/p22 pin function of txd01/p23 pin port function (p22) serial function (rxd01) port function (p22) serial function (rxd01) port function (p23) serial function (txd01) chapter 12 serial interfaces uart00 and uart01 237 user? manual u13029ej7v1ud (b) asynchronous serial interface status registers 0, 1 (asis00, asis01) asis00 and asis01 can be read with an 8-bit memory manipulation instruction. reset input clears these registers to 00h. notes 1. even if the stop bit length is set to 2 bits using bit 2 (sl0n) of asynchronous serial interface mode register n (asim0n), only 1 stop bit is detected during reception. 2. if an overrun error occurs, be sure to read receive buffer register n (rxb0n). until rxb0n is read, an overrun error persistently occurs each time data is received. remark n = 0, 1 6543210 7 symbol asis0n 0 0 0 0 0 pe0n fe0n ove0n ffa1h, 00h r ffa9h address after reset r/w parity error flag pe0n 0 1 parity error does not occur. parity error occurs (transmit data parity specification and receive data parity do not match). framing error flag fe0n 0 1 framing error does not occur. framing error occurs note 1 (stop bit not detected). overrun error flag ove0n 0 1 overrun error does not occur. overrun error occurs note 2 (next receive completed before data is read from receive buffer register). chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 238 (c) baud rate generator control registers 0, 1 (brgc00, brgc01) brgc00 and brgc01 are set by an 8-bit memory manipulation instruction. reset input clears these registers to 00h. note expanded-specification products only. cautions 1. if a write to brgc00 is performed during communication, the output of the baud rate generator may be disrupted, preventing normal communication from continuing. brgc00 should therefore not be written to during communication. 2. set brgc00 to 00h in the infrared data transfer mode. remarks 1. f x : system clock oscillation frequency 2. f sck : 5-bit counter source clock 3. k: value set in bits mdl000 to mdl003 (0 k 14) 6543210 7 symbol brgc00 0 tps002 tps001 tps000 mdl003 mdl002 mdl001 mdl000 ffa2h 00h r/w address after reset r/w 0 0 6 mhz 3 mhz 1.5 mhz 93.7 khz 0 187 khz 1 1 46.8 khz 0 0 1 0 1 0 1 0 1 0 tps002 5-bit counter source clock selection tps001 tps000 375 khz 750 khz 0 1 1 0 1 0 111 0 0 f sck /16 f sck /17 f sck /18 f sck /22 0 f sck /21 0 0 f sck /23 0 0 0 1 1 0 0 1 0 1 mdl003 baud rate generator input clock selection mdl002 mdl001 f sck /20 f sck /19 0 0 0 1 1 0 011 0 1 0 1 0 mdl000 1 0 1 k 0 1 2 5 6 3 4 7 1 1 f sck /24 f sck /25 f sck /26 f sck /30 1 f sck /29 1 1 setting prohibited 0 0 0 1 1 0 0 1 0 1 f sck /28 f sck /27 1 1 0 1 1 0 111 0 1 0 1 0 1 0 1 8 9 10 13 14 11 12 f x /2 f x /2 2 f x /2 3 f x /2 7 f x /2 6 f x /2 8 f x /2 5 f x /2 4 4.19 mhz 2.1 mhz 1.05 mhz 65.5 khz 131 khz 32.7 khz 262 khz 524 khz at f x = 12 mhz note at f x = 8.38 mhz chapter 12 serial interfaces uart00 and uart01 239 user? manual u13029ej7v1ud caution if a write to brgc01 is performed during communication, the output of the baud rate generator may be disrupted, preventing normal communication from continuing. brgc01 should therefore not be written to during communication. remarks 1. f x : system clock oscillation frequency 2. f sck : 5-bit counter source clock 3. k: value set in bits mdl010 to mdl013 (0 k 14) 6543210 7 symbol brgc01 0 tps012 tps011 tps010 mdl013 mdl012 mdl011 mdl010 ffaah 00h r/w address after reset r/w 0 0 f x /2 4 f x /2 5 f x /2 6 0 f x /2 9 1 1 0 0 1 0 1 0 1 0 1 0 tps012 5-bit counter source clock selection tps011 tps010 f x /2 8 f x /2 7 0 1 1 0 1 0 111 0 0 f sck /16 f sck /17 f sck /18 f sck /22 0 f sck /21 0 0 f sck /23 0 0 0 1 1 0 0 1 0 1 mdl013 baud rate generator input clock selection mdl012 mdl011 f sck /20 f sck /19 0 0 0 1 1 0 011 0 1 0 1 0 mdl010 1 0 1 k 0 1 2 5 6 3 4 7 1 1 f sck /24 f sck /25 f sck /26 f sck /30 1 f sck /29 1 1 setting prohibited 0 0 0 1 1 0 0 1 0 1 f sck /28 f sck /27 1 1 0 1 1 0 111 0 1 0 1 0 1 0 1 8 9 10 13 14 11 12 f x /2 2 f x /2 3 524 khz 262 khz 131 khz 16.4 khz 32.7 khz 65.5 khz 2 mhz 1 mhz 750 khz 375 khz 187 khz 23.4 khz 46.8 khz 93.7 khz 3 mhz 1.5 mhz at f x = 8.38 mhz at f x = 12 mhz note note expanded-specification products only. chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 240 the transmit/receive clock for the baud rate to be generated is obtained by dividing the system clock. generating transmit/receive clock for baud rate from system clock the transmit/receive clock is generated by dividing the system clock. the baud rate generated from the system clock can be calculated from the following expression. [baud rate] = [hz] f x : system clock oscillation frequency m: value set by tps0n0 to tps0n2 (n = 0, 1) (1 m 8 for uart00, 2 m 9 for uart01) k: value set by mdl0n0 to mdl0n3 (n = 0, 1) (0 k 14) tables 12-2 and 12-3 show the relationship between the source clock of the 5-bit counter and the value of m. table 12-4 shows the relationship between the system clock and baud rate. table 12-2. relationship between source clock of 5-bit counter and value of m (with uart00) note expanded-specification products only. table 12-3. relationship between source clock of 5-bit counter and value of m (with uart01) note expanded-specification products only. f x 2 m + 1 (k + 16) 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 tps002 5-bit counter source clock selection tps001 tps000 0 1 1 0 1 0 111 m 1 2 3 6 7 4 5 8 6 mhz 3 mhz 1.5 mhz 93.7 khz 187 khz 46.8 khz 375 khz 750 khz 4.19 mhz 2.1 mhz 1.05 mhz 65.5 khz 131 khz 32.7 khz 262 khz 524 khz at f x = 12 mhz note at f x = 8.38 mhz f x /2 f x /2 2 f x /2 3 f x /2 7 f x /2 6 f x /2 8 f x /2 5 f x /2 4 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 tps012 5-bit counter source clock selection tps011 tps010 0 1 1 0 1 0 111 2 3 4 7 8 m 5 6 9 524 khz 262 khz 131 khz 16.4 khz 32.7 khz 65.5 khz 2 mhz 1 mhz 750 khz 375 khz 187 khz 23.4 khz 46.8 khz 93.7 khz 3 mhz 1.5 mhz at f x = 8.38 mhz at f x = 12 mhz note f x /2 4 f x /2 5 f x /2 6 f x /2 9 f x /2 8 f x /2 7 f x /2 2 f x /2 3 chapter 12 serial interfaces uart00 and uart01 241 user? manual u13029ej7v1ud table 12-4. relationship between system clock and baud rate 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 76,800 115,200 153,600 7bh 6bh 5bh 4bh 3bh 2bh 21h 1bh 0bh 02h 7bh 6bh 5bh 4bh 3bh 2bh 1bh 11h 0bh 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 ?.31 1.14 1.10 1.10 1.10 1.10 1.10 1.10 1.10 ?.34 1.10 1.10 1.10 7ah 6ah 5ah 4ah 3ah 2ah 20h 1ah 0ah 01h 7ah 6ah 5ah 4ah 3ah 2ah 1ah 10h 0ah 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 2.12 78h 68h 58h 48h 38h 28h 1bh 18h 08h 00h 78h 68h 58h 48h 38h 28h 18h 0bh 08h 0 0 0 0 0 0 0 1.69 0 0 0 70h 60h 50h 40h 30h 20h 14h 10h 00h 70h 60h 50h 40h 30h 20h 10h 04h 00h 7bh 6bh 5bh 4bh 3bh 2bh 1bh 11h 0bh 7bh 6bh 5bh 4bh 3bh 2bh 1bh 0bh 01h 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 system clock f x (mhz) 8.386 8.000 7.3728 5.000 4.1943 70h 60h 50h 40h 30h 24h 20h 10h 06h 00h 70h 60h 50h 40h 30h 20h 14h 10h 00h 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 ?.36 1.73 79h 69h 59h 49h 39h 2dh 29h 19h 0fh 04h 74h 64h 54h 44h 34h 24h 18h 14h 04h ?.34 ?.34 ?.34 ?.34 ?.34 ?.34 0 ?.34 ?.34 0.16 ?.34 baud rate (bps) brgc 00 brgc 01 error (%) brgc 00 brgc 01 error (%) brgc 00 brgc 01 error (%) brgc 00 brgc 01 error (%) brgc 00 brgc 01 error (%) brgc 00 brgc 01 error (%) brgc 00 brgc 01 error (%) 12.000 note 10.000 note note expanded-specification products only. chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 242 range of baud rate tolerance the range of baud rate tolerance depends on the number of bits in one frame and division ratio of the counter [1/(16 + k)]. figure 12-11 shows an example of baud rate tolerance. figure 12-11. baud rate tolerance including sampling error (when k = 0) remark t: source clock cycle of 5-bit counter baud rate tolerance (when k = 0) = 15.5/320 100 = 4.8438 (%) basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t? enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t? enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t chapter 12 serial interfaces uart00 and uart01 243 user? manual u13029ej7v1ud one data frame consists of following bits: start bits .................. 1 bit character bits ......... 7 bits/8 bits parity bits ................ even parity/odd parity/0 parity/no parity stop bits .................. 1 bit/2 bits the character bit length, parity bit and stop bit length for each data frame is specified by asynchronous serial interface mode register n (asim0n). when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always 0. the serial transfer rate is selected by means of baud rate generator control register n (brgc0n). if a serial data receive error is generated, the receive error contents can be determined by reading the status of asynchronous serial interface status register n (asis0n). remark n = 0, 1 (2) communication operation (a) data format figure 12-12 shows transmit/receive data format. figure 12-12. asynchronous serial interface transmit/receive data format d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame character bit chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 244 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receiving side. with even parity and odd parity, a one-bit (odd number) error can be detected. with 0 parity and no parity, an error cannot be detected. (i) even parity transmission the number of bits with a value of ?? including the parity bit, in the transmit data is controlled to be even. the value of the parity bit is as follows: number of bits with a value of ??in transmit data is odd: 1 number of bits with a value of ??in transmit data is even: 0 reception the number of bits with a value of ?? including the parity bit, in the receive data is counted. if it is odd, a parity error occurs. (ii) odd parity transmission conversely to the situation with even parity, the number of bits with a value of ?? including the parity bit, in the transmit data is controlled to be odd. the value of the parity bit is as follows: number of bits with a value of ??in transmit data is odd: 0 number of bits with a value of ??in transmit data is even: 1 reception the number of bits with a value of ?? including the parity bit, in the receive data is counted. if it is even, a parity error occurs. (iii) 0 parity when transmitting, the parity bit is set to 0 irrespective of the transmit data. at reception, a parity bit check is not performed. therefore, a parity error is not generated, irrespective of whether the parity bit is set to 0 or 1. (iv) no parity a parity bit is not added to the transmit data. at reception, data is received assuming that there is no parity bit. since there is no parity bit, a parity error is not generated. chapter 12 serial interfaces uart00 and uart01 245 user? manual u13029ej7v1ud (c) transmission a transmit operation is enabled by setting the txe0n bit of asynchronous serial interface mode n (asim0n) to 1 and is started by writing transmit data to transmit shift register n (txs0n). the start bit, parity bit and stop bit(s) are added automatically. when transmit operation starts, the data in transmit shift register n (txs0n) is shifted out, and when transmit shift register n (txs0n) is empty, a transmission completion interrupt request (intstn) is generated. figure 12-13. timing of asynchronous serial interface transmission completion interrupt request generation (a) stop bit length: 1 (b) stop bit length: 2 caution rewriting of asynchronous serial interface mode register n (asim0n) should not be performed during a transmit operation. if rewriting of the asim0n register is performed during transmission, subsequent transmit operations may not be possible (the normal state is restored by reset input). it is possible to determine whether transmission is in progress by software by using a transmission completion interrupt request (intstn) or the interrupt request flag (stifn) set by intstn. remark n = 0, 1 d1 d2 d6 d7 parity d0 txd0n (output) intstn stop start d1 d2 d6 d7 parity d0 txd0n (output) intstn start stop chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 246 (d) reception when the rxe0n bit of asynchronous serial interface mode register n (asim0n) is set (1), a receive operation is enabled and sampling of the rxd0n pin input is performed. rxd0n pin input sampling is performed using the serial clock specified by asim0n. when the rxd0n pin input becomes low, the 5-bit counter of the baud rate generator starts counting, and at the time when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. if the rxd0n pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is performed. when character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends. when one frame of data has been received, the receive data in the shift register is transferred to receive buffer register n (rxb0n), and a reception completion interrupt request (intsrn) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb0n. intsrn is generated if bit 1 (isrm0n) of asim0n is cleared (0) on occurrence of the error. if the isrm0n bit is set (1), intsrn is not generated. if the rxe0n bit is reset (0) during the receive operation, the receive operation is stopped immediately. in this case, the contents of rxb0n and asis0n are not changed, and intsrn and intser0 are not generated. figure 12-14. timing of asynchronous serial interface reception completion interrupt request generation d1 d2 d6 d7 parity d0 rxd0n (input) intsrn stop start caution receive buffer register n (rxb0n) must be read even if a receive error occurs. if rxb0n is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. remark n = 0, 1 chapter 12 serial interfaces uart00 and uart01 247 user? manual u13029ej7v1ud (e) receive errors the three types of errors during receive operations are the parity error, framing error and overrun error. with the uart00, setting the data receive result error flag in asynchronous serial interface status register 0 (asis00) generates a receive error interrupt request (intser0). the receiver error interrupt request is generated before the receive complete interrupt request (intsr0). with the uart01, the receiver error interrupt request is not generated. table 12-5 shows the causes of receive errors. reading the data in asis0n makes it possible to ascertain what error has occurred during reception (see figures 12-14 and 12-15 ). the contents of asis0n are reset (0) by reading receive buffer register n (rxb0n) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 12-5. receive error causes receive error cause asis0n value parity error transmission-time parity specification and reception data parity do not match 04h framing error stop bit not detected 02h overrun error reception of next data is completed before data is read from receive buffer register 01h figure 12-15. receive error timing d1 d2 d6 d7 parity d0 rxd0n (input) intsrn note 1 stop start intser0 note 2 (on occurrence of framing/overrun error) intser0 note 2 (on occurrence of parity error) notes 1. intsrn is not generated if a receive error occurs when the isrm0n bit is set (1). 2. the receive error interrupt request is not generated with uart01. cautions 1. the contents of asis0n are reset (to 0) by reading receive buffer register n (rxb0n) or receiving the next data. to ascertain the error contents, asis0n must be read before reading rxb0n. 2. receive buffer register n (rxb0n) must be read even if a receive error has occurred. if rxb0n is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. remark n = 0, 1 chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 248 12.4.3 infrared data transfer mode caution the infrared data transfer mode can only be used with uart00. in the infrared data transfer mode, pulses can be output and received in the following data format. remark the sir standard is not supported (negotiation at 9,600 bps cannot be performed). (1) data format figure 12-16 shows the data format of the infrared data transfer mode in comparison with the data format in uart mode. the ir frame corresponds to the bit string of the uart frame that consists of a start bit, 8 data bits and 1 stop bit. the length of the electrical pulse transmitted or received in the ir frame is 3/16 of a 1-bit cycle. the pulse 3/16 of a 1-bit cycle rises in the middle of the bit cycle (refer to the figure below). figure 12-16. comparison of data format in infrared data transfer mode and uart mode pulse width = 3/16 bit time bit time 0 start bit 1 d0 1 stop bit 0 d1 1 d2 0 d3 0 d4 1 d5 1 d6 0 d7 start bit stop bit 10 100110 uart frame data bit ir frame data bit pulse width = 3/16 bit time bit time 0 1 chapter 12 serial interfaces uart00 and uart01 249 user? manual u13029ej7v1ud (2) bit rate and pulse width table 12-6 shows the values of the bit rate, bit rate tolerance, and pulse width. table 12-6. bit rate and pulse width bit rate bit rate tolerance minimum pulse width nominal value of pulse maximum pulse (kbits/s) (% of bit rate) ( s) note 2 width 3/16 ( s) width ( s) 115.2 note 1 0.87 1.41 1.63 2.71 notes 1. f x = @ 7.3728 mhz operation 2. where a digital noise eliminator is used with the microcontroller at a frequency of 1.41 mhz or higher caution set baud rate generator control register 0 (brgc00) to 00h in the infrared data transfer mode. remark f x : system clock oscillation frequency (3) baud rate that can be set in infrared data transfer mode table 12-7. baud rate that can be set in infrared data transfer mode system clock f x (mhz) baud rate (bps) 12.000 note 187,500 note 8.386 131,031 8.000 125,000 7.3728 115,200 5.000 78,125 4.1943 65,536 note expanded-specification products only. chapter 12 serial interfaces uart00 and uart01 user? manual u13029ej7v1ud 250 (4) i/o data and internal signal transmission timing reception timing data reception is delayed by half the set baud rate. start bit uart00 transfer data rxd00 input edge detection sampling clock reception rate conversion data sampling timing stop bit start bit uart00 output data uart00 (inverted data) infrared data transfer enable signal txd00 pin output signal stop bit 251 user? manual u13029ej7v1ud chapter 13 serial interface sio3 13.1 function of serial interface sio3 s erial interface sio3 has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. for details, see 13.4.1 operation stop mode . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck), serial output line (so), and serial input line (si). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit of the serial transferred 8-bit data is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o incorporating a clock-synchronous serial interface, a display controller, etc. chapter 13 serial interface sio3 user? manual u13029ej7v1ud 252 13.2 configuration of serial interface s erial interface sio3 includes the following hardware. table 13-1. configuration of serial interface 3 item configuration register serial i/o shift register 3 (sio3) control register serial operation mode register 3 (csim3) figure 13-1. block diagram of serial interface 3 (1) serial i/o shift register 3 (sio3) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) in synchronization with the serial clock. sio3 is set by an 8-bit memory manipulation instruction. when bit 7 (csie3) of serial operation mode register 3 (csim3) is set to 1, a serial operation can be started by writing data to or reading data from sio3. when transmitting, data written to sio3 is output to the serial output (so). when receiving, data is read from the serial input (si) and written to sio3. reset input makes sio3 undefined. caution do not access sio3 during a transfer operation unless the access is triggered by a transfer start (read operations are disabled when mode = 0 and write operations are disabled when mode = 1). internal bus interrupt request signal generator selector serial clock counter serial clock controller serial i/o shift register 3 (sio3) si/p52 so/p53 sck/p51 intcsi3 f x /2 6 f x /2 7 f x /2 8 chapter 13 serial interface sio3 253 user? manual u13029ej7v1ud 13.3 register controlling serial interface s erial interface sio3 is controlled by the following register. serial operation mode register 3 (csim3) (1) serial operation mode register 3 (csim3) this register is used to enable or disable the sio3 serial clock, operation modes, and specific operations. csim3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim3 to 00h. caution when using the 3-wire serial i/o mode, set the port mode registers (pm5x) as shown below. also, set the respective output latches to 0. for serial clock output (master transmit/receive) set p51 (sck) to the output mode (pm51 = 0). for serial clock input (slave transmit/receive) set p51 to the input mode (pm51 = 1). for transmit/transmit and receive mode set p53 (so) to the output mode (pm53 = 0). set p52 (si) to the input mode (pm52 = 1) (in transmit/receive mode). for receive mode set p52 (si) to the input mode (pm52 = 1). chapter 13 serial interface sio3 user? manual u13029ej7v1ud 254 figure 13-2. format of serial operation mode register 3 csie3 enable/disable specification for sio3 shift register operation serial counter port 0 operation disabled cleared port function note 1 1 operation enabled count operation enabled serial function + port function note 2 mode transfer operation modes and flags operation mode transfer start trigger so output 0 transmit/transmit and receive mode write to sio3 normal output 1 receive-only mode read from sio3 fixed at low level scl31 scl30 clock selection at f x = 12 mhz note 3 at f x = 8.38 mhz 00 external clock input to sck pin 01f x /2 6 187 khz 131 khz 10f x /2 7 93.7 khz 65.5 khz 11f x /2 8 46.8 khz 32.7 khz notes 1. when csie3 = 0 (sio3 operation stopped), the si, so, and sck pins can be used for port functions. 2. when csie3 = 1 (sio3 operation enabled), if only the transmit function is used, the si pin can be used for a port function, and in the receive-only mode, the so pin can be used for a port function. 3. expanded-specification products only remark f x : system clock oscillation frequency csie3 0 0 mode scl31scl30 csim3 ffb0h 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 0 chapter 13 serial interface sio3 255 user? manual u13029ej7v1ud 13.4 operation of serial interface this section explains the two modes of serial interface sio3. 13.4.1 operation stop mode because serial transfer is not performed during this mode, the power consumption can be reduced. in addition, pins can be used as normal i/o ports. (1) register settings operation stop mode is set by serial operation mode register 3 (csim3). csim3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim3 to 00h. csie3 enable/disable specification for sio3 shift register operation serial counter port 0 operation disabled cleared port function note 1 1 operation enabled count operation enabled serial function + port function note 2 notes 1. when csie3 = 0 (sio3 operation stopped), the si, so, and sck pins can be used for port functions. 2. when csie3 = 1 (sio3 operation enabled), if only the transmit function is used, the si pin can be used for a port function, and in the receive-only mode, the so pin can be used for a port function. csie3 0 0 mode scl31scl30 csim3 ffb0h 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 0 chapter 13 serial interface sio3 user? manual u13029ej7v1ud 256 13.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection to a peripheral i/o incorporating a clock-synchronous serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sck), serial output line (so), and serial input line (si). (1) register settings the 3-wire serial i/o mode is set by serial operation mode register 3 (csim3). csim3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets csim3 to 00h. caution when using the 3-wire serial i/o mode, set the port mode registers (pm5x) as shown below. also, set the respective output latches to 0. for serial clock output (master transmit/receive) set p51 (sck) to the output mode (pm51 = 0). for serial clock input (slave transmit/receive) set p51 to the input mode (pm51 = 1). for transmit/transmit and receive mode set p53 (so) to the output mode (pm53 = 0). set p52 (si) to the input mode (pm52 = 1) (in transmit/receive mode). for receive mode set p52 (si) to the input mode (pm52 = 1). chapter 13 serial interface sio3 257 user? manual u13029ej7v1ud csie3 0 0 mode scl31scl30 csim3 ffb0h 00h r/w 54 symbol address after reset r/w 0 76 32 0 1 0 csie3 enable/disable specification for sio3 shift register operation serial counter port 0 operation disabled cleared port function note 1 1 operation enabled count operation enabled serial function + port function note 2 mode transfer operation modes and flags operation mode transfer start trigger so output 0 transmit/transmit and receive mode write to sio3 normal output 1 receive-only mode read from sio3 fixed at low level scl31 scl30 clock selection at f x = 12 mhz note 3 at f x = 8.38 mhz 00 external clock input to sck pin 01f x /2 6 187 khz 131 khz 10f x /2 7 93.7 khz 65.5 khz 11f x /2 8 46.8 khz 32.7 khz notes 1. when csie3 = 0 (sio3 operation stopped), the si, so, and sck pins can be used for port functions. 2. when csie3 = 1 (sio3 operation enabled), if only the transmit function is used, the si pin can be used for a port function, and in the receive-only mode, the so pin can be used for a port function. 3. expanded-specification products only remark f x : system clock oscillation frequency chapter 13 serial interface sio3 user? manual u13029ej7v1ud 258 (2) communication operations in the 3-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is transmitted or received in synchronization with the serial clock. serial i/o shift register 3 (sio3) is shifted in synchronization with the falling edge of the serial clock. transmission data is held in the so latch and is output from the so pin. data that is received via the si pin in synchronization with the rising edge of the serial clock is latched to sio3. completion of an 8-bit transfer automatically stops operation of sio3 and sets an interrupt request flag (csiif3). figure 13-3. timing of 3-wire serial i/o mode (3) transfer start a serial transfer starts when the following conditions have been satisfied and transfer data has been set (or read) to serial i/o shift register 3 (sio3). the sio3 operation control bit (csie3) = 1 after an 8-bit serial transfer, either the internal serial clock is stopped or sck is set to high level. transmit/transmit and receive mode when csie3 = 1 and mode = 0, transfer starts when writing to sio3. receive-only mode when csie3 = 1 and mode = 1, transfer starts when reading from sio3. caution after data has been written to sio3, transfer will not start even if the csie3 bit value is set to 1. completion of an 8-bit transfer automatically stops the serial transfer operation and sets an interrupt request flag (csiif3). sck si so csiif3 transfer starts in synchronization with the sck falling edge transfer completion 1234 5 678 di7 di6 di5 do7 do6 do5 di4 di3 di2 do4 do3 do2 di1 di0 do1 do0 259 user? manual u13029ej7v1ud chapter 14 interrupt functions 14.1 types of interrupt functions the following three types of interrupt functions are available. (1) non-maskable interrupt this interrupt is unconditionally acknowledged even in the interrupt disabled status. it is not subject to interrupt priority control and therefore takes precedence over all interrupt requests. this interrupt generates a standby release signal. one interrupt request from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupts these interrupts are subject to mask control, and can be divided into two groups according to the setting of the priority specification flag register (pr0l, pr0h, pr1l): one with higher priority and the other with lower priority. higher-priority interrupts can nest lower-priority interrupts. the priority when two or more interrupt requests with the same priority occur at the same time is predetermined (refer to table 14-1 ). this interrupt generates a standby release signal. eight external interrupt requests and sixteen internal interrupt requests are incorporated as maskable interrupts. (3) software interrupt this is a vectored interrupt generated when the brk instruction is executed and can be acknowledged even in the interrupt disabled status. this interrupt is not subject to interrupt priority control. 14.2 interrupt sources and configuration a total of 26 interrupt sources including non-maskable, maskable, and software interrupt sources are available (refer to table 14-1 ). remark there are two types of interrupt sources for the watchdog timer (intwdt): non-maskable interrupts and maskable interrupts (internal). only one of these interrupts can be selected. chapter 14 interrupt functions user? manual u13029ej7v1ud 260 table 14-1. interrupt source list (1/2) interrupt type default priority internal/ external note 1 vector table address basic configuration type note 2 trigger name interrupt source 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 watchdog timer overflow (when non- maskable interrupt is selected) watchdog timer overflow (when interval timer mode is selected) pin input edge detection tm7 underflow tm00 and cr000 match signal generation (when compare register is specified) ti010 valid edge detection (when the capture register is specified) tm00 and cr010 match signal generation (when compare register is specified) ti000 valid edge detection (when the capture register is specified) tm01 and cr001 match signal generation (when compare register is specified) ti011 valid edge detection (when the capture register is specified) tm01 and cr011 match signal generation (when compare register is specified) ti001 valid edge detection (when the capture register is specified) uart00 receive error generation end of uart00 reception end of uart00 transmission end of uart01 reception end of uart01 transmission 0004h 0006h 0008h 000ah 000ch 000eh 0010h 0012h 0014h 0016h 0018h 001ah 001ch 001eh 0020h 0022h 0024h 0026h 0028h (a) (b) (c) (b) intwdt intwdt intp0 intp1 intp2 intp3 intp4 intp5 intp6 intp7 inttm7 inttm000 inttm010 inttm001 inttm011 intser0 intsr0 intst0 intsr1 intst1 internal external internal notes 1. the default priority is the priority applicable when more than one maskable interrupt is generated at the same time. 0 is the highest priority and 23 the lowest. 2. basic configuration types (a) to (d) correspond to (a) to (d) on the next pages. non- maskable maskable chapter 14 interrupt functions 261 user? manual u13029ej7v1ud interrupt type default priority internal/ external note 1 vector table address basic configuration type note 2 trigger name interrupt source 19 20 21 22 23 tm50 and cr50 match signal generation tm51 and cr51 match signal generation tm52 and cr52 match signal generation end of sio3 transfer end of a/d conversion execution of brk instruction 002ah 002ch 002eh 0030h 0032h 003eh (b) (d) inttm50 inttm51 inttm52 intcsi3 intad0 brk internal maskable software notes 1. the default priority is the priority applicable when more than one maskable interrupt is generated at the same time. 0 is the highest priority and 23 the lowest. 2. basic configuration types (a) to (d) correspond to (a) to (d) on the next pages. table 14-1. interrupt source list (2/2) chapter 14 interrupt functions user? manual u13029ej7v1ud 262 figure 14-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt internal bus vector table address generator priority controller interrupt request standby release signal internal bus mk ie pr isp standby release signal if interrupt request vector table address generator priority controller internal bus mk ie pr isp standby release signal if interrupt request edge detector external interrupt rising/falling edge enable register (egp, egn, egp5, egn5) vector table address generator priority controller chapter 14 interrupt functions 263 user? manual u13029ej7v1ud figure 14-1. basic configuration of interrupt function (2/2) (d) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag internal bus interrupt request vector table address generator chapter 14 interrupt functions user? manual u13029ej7v1ud 264 14.3 registers controlling interrupt functions the following eight types of registers control the interrupt functions. interrupt request flag registers (if0l, if0h, if1l) interrupt mask flag registers (mk0l, mk0h, mk1l) priority specification flag registers (pr0l, pr0h, pr1l) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) external interrupt rising edge enable register 5 (egp5) external interrupt falling edge enable register 5 (egn5) program status word (psw) table 14-2 shows the names of the interrupt request flags, interrupt mask flags, and priority specification flags corresponding to the respective interrupt request sources. table 14-2. flags corresponding to respective interrupt request sources interrupt source interrupt request flag interrupt mask flag priority specification flag register register register intwdt wdtif note if0l wdtmk note mk0l wdtpr note pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intp6 pif6 pmk6 ppr6 intp7 pif7 if0h pmk7 mk0h ppr7 pr0h inttm7 tmif7 tmmk7 tmpr7 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 inttm001 tmif001 tmmk001 tmpr001 inttm011 tmif011 tmmk011 tmpr011 intser0 serif0 sermk0 serpr0 intsr0 srif0 srmk0 srpr0 intst0 stif0 if1l stmk0 mk1l stpr0 pr1l intsr1 srif1 srmk1 srpr1 intst1 stif1 stmk1 stpr1 inttm50 tmif50 tmmk50 tmpr50 inttm51 tmif51 tmmk51 tmpr51 inttm52 tmif52 tmmk52 tmpr52 intcsi3 csiif3 csimk3 csipr3 intad0 adif0 admk0 adpr0 note interrupt control flag when the watchdog timer is used as an interval timer chapter 14 interrupt functions 265 user? manual u13029ej7v1ud (1) interrupt request flag registers (if0l, if0h, if1l) an interrupt request flag is set to 1 when the corresponding interrupt request is generated or when an instruction is executed, and is cleared to 0 when the interrupt request is acknowledged, when the reset signal is input, or when an instruction is executed. if0l, if0h, and if1l are set by a 1-bit or 8-bit memory manipulation instruction. when using if0l and if0h as a 16-bit register, if0, it is set by a 16-bit memory manipulation instruction. reset input clears these registers to 00h. figure 14-2. format of interrupt request flag registers cautions 1. the wdtif flag can be read/written only when the watchdog timer is used as an interval timer. clear the wdtif flag to 0 when watchdog timer mode 1 is used. 2. before restarting the timer, serial interface, or a/d converter in the standby mode, be sure to clear the interrupt request flag. note that noise may cause an interrupt request flag to be set. 3. when an interrupt is acknowledged, the interrupt request flag is automatically cleared, and then the interrupt routine is started. if1l csiif3 tmif51 tmif50 stif1 srif1 stif0 if0h srif0 serif0 tmi f011 tmif001 tmif010 tmif000 tmif7 pif7 ffe1h 00h r/w ffe2h 00h r/w tmif52 adif0 if 0 1 interrupt request flag interrupt request signal is not generated. interrupt request signal is generated and interrupt is requested. 6543210 7 5 3210 64 7 if0l pif6 pif5 pif4 pif3 pif2 pif1 pif0 wdtif symbol ffe0h 00h r/w address after reset r/w 6543210 7 chapter 14 interrupt functions user? manual u13029ej7v1ud 266 cautions 1. if the watchdog timer is used in watchdog timer mode 1, the wdtmk flag will be undefined when read. 2. because port 0 and p54 to p57 have alternate functions of external interrupt request inputs, the corresponding interrupt request flag is set when the output mode is specified and output level of a port pin is changed. to use the port in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance. mk1l tmmk 52 tmmk 50 stmk0 srmk1 stmk1 mk0h tmmk 001 tmmk 010 tmmk 000 tmmk 011 srmk0 sermk0 tmmk7 pmk7 ffe5h ffh r/w ffe6h ffh r/w tmmk 51 admk0 csimk3 interrupt servicing control mk 0 1 enables interrupt servicing disables interrupt servicing 6543210 7 5 3210 64 7 mk0l pmk3 pmk2 pmk1 pmk6 pmk5 pmk4 pmk0 wdtmk symbol ffe4h ffh r/w address after reset r/w 6543210 7 (2) interrupt mask flag registers (mk0l, mk0h, mk1l) an interrupt mask flag enables or disables the corresponding maskable interrupt servicing and release of the standby mode. mk0l, mk0h, and mk1l are set by a 1-bit or 8-bit memory manipulation instruction. when using mk0l and mk0h as a 16-bit register, mk0, it is set by a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 14-3. format of interrupt mask flag register chapter 14 interrupt functions 267 user? manual u13029ej7v1ud pr1l tmpr 51 tmpr 50 stpr 1 srpr 1 stpr 0 pr0h srpr 0 serpr 0 tmpr 011 tmpr 001 tmpr 010 tmpr 000 tmpr7 ppr7 ffe9h ffh r/w ffeah ffh r/w adpr0 csipr3 pr 0 priority level selection high priority level low priority level tmpr 52 1 6543210 7 3 2 1 0 654 7 pr0l ppr3 ppr2 ppr1 ppr6 ppr5 ppr4 ppr0 wdtpr symbol ffe8h ffh r/w address after reset r/w 6543210 7 (3) priority specification flag registers (pr0l, pr0h, pr1l) a priority specification flag sets the priority of the corresponding maskable interrupt. pr0l, pr0h, and pr1l are set by a 1-bit or 8-bit memory manipulation instruction. when using pr0l and pr0h as a 16-bit register, pr0, it is set by a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 14-4. format of priority specification flag register caution to use the watchdog timer in watchdog timer mode 1, set the wdtpr flag to 1. chapter 14 interrupt functions user? manual u13029ej7v1ud 268 (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) egp and egn specify the valid edge to be detected on pins p00 to p03. egp and egn can be read or written to with a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 14-5. format of external interrupt rising edge enable register and external interrupt falling edge enable register 6543210 7 symbol egn 0 0 0 0 egn3 egn2 egn1 egn0 egpn 0 0 1 valid edge of intpn pin (n = 0 to 3) interrupt disable falling edge rising edge egnn 0 1 0 1 both rising and falling edges 1 ff49h 00h r/w address after reset r/w 6543210 7 symbol egp 0 0 0 0 egp3 egp2 egp1 egp0 ff48h 00h r/w address after reset r/w chapter 14 interrupt functions 269 user? manual u13029ej7v1ud (5) external interrupt rising edge enable register 5 (egp5), external interrupt falling edge enable register 5 (egn5) egp5 and egn5 specify the valid edge to be detected on pins p54 to p57. egp5 and egn5 can be read or written to with a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 14-6. format of external interrupt rising edge enable register 5 and external interrupt falling edge enable register 5 6543210 7 symbol egn5 egn57 egn56 egn55 egn54 0 000 egp5n 0 0 1 valid edge of intpn pin (n = 4 to 7) interrupt disable falling edge rising edge egn5n 0 1 0 1 both rising and falling edges 1 ff7dh 00h r/w address after reset r/w 6543210 7 symbol egp5 egp57 egp56 egp55 egp54 0 000 ff7ch 00h r/w address after reset r/w chapter 14 interrupt functions user? manual u13029ej7v1ud 270 (6) program status word (psw) the program status word is a register that holds the instruction execution result and current status of interrupt request. an ie flag that enables/disables the maskable interrupts and an isp flag that controls multiple interrupts processing are mapped to this register. this register can be read or written in 8-bit units. in addition, it can also be manipulated by using a bit manipulation instruction or dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, and when the brk instruction is executed, the contents of the psw are automatically saved to the stack. at this time, the ie flag is reset to 0. if a maskable interrupt request has been acknowledged, the contents of the priority flag of that interrupt are transferred to the isp flag. the contents of the psw can also be saved to the stack by the push psw instruction, and restored from the stack by reti, retb, or pop psw instruction. reset input sets the psw to 02h. figure 14-7. configuration of program status word 14.4 interrupt servicing operation 14.4.1 non-maskable interrupt request acknowledgement operation the non-maskable interrupt request is unconditionally acknowledged even when interrupt requests are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, the contents are saved to the stack, program status word (psw) and program counter (pc), in that order, the ie flag and isp flag are reset to 0, the contents of the vector table are loaded to the pc, and then program execution branches. if a new non-maskable interrupt request is generated while the non-maskable interrupt service program is being executed, the interrupt request is acknowledged when the current execution of the non-maskable interrupt service program is complete (after the reti instruction has been executed) and one instruction in the main routine has been executed. if two or more new non-maskable interrupt requests are generated while the non-maskable interrupt service program is being executed, only one non-maskable interrupt request is acknowledged after execution of the non- maskable interrupt service program is complete. figure 14-8 shows the flowchart from non-maskable interrupt request generation to acknowledgement, figure 14- 9 shows the timing of non-maskable interrupt request acknowledgement, and figure 14-10 shows the acknowledgement operation when multiple non-maskable interrupt requests are generated. 0 6543210 7 psw ie z rbs1 ac rbs0 0 isp cy 02h after reset ie 0 1 interrupt request acknowledge enable/disable disables enables isp priority of interrupt currently processed interrupt with higher priority is processed (interrupt with lower priority is disabled). interrupt is not acknowledged, or interrupt with lower priority is processed (all maskable interrupts are enabled). used when normal instruction is executed 1 symbol chapter 14 interrupt functions 271 user? manual u13029ej7v1ud figure 14-8. flowchart from non-maskable interrupt request generation to acknowledgement instruction instruction saving psw and pc, and jumping to interrupt servicing interrupt servicing program cpu processing wdtif interrupt request generated during this interval is acknowledged at . start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated wdt interrupt is not processed interrupt request pending no yes interrupt control register is not accessed yes no yes interrupt servicing is started wdtm3 = 0 (non-maskable interrupt request is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 14-9. timing of non-maskable interrupt request acknowledgement wdtif: watchdog timer interrupt request flag chapter 14 interrupt functions user? manual u13029ej7v1ud 272 figure 14-10. acknowledgement operation of non-maskable interrupt request (a) when new non-maskable interrupt request is generated while non-maskable interrupt service program is being executed (b) if two new non-maskable interrupt requests are generated while non-maskable interrupt service program is being executed main routine nmi request <1> 1 instruction ex ecution nmi request <2> nmi request <1> execution nmi request <2> pending nmi request <3> pending p ending nmi request <2> processing nmi request <3> nmi request <3> is not acknowledged (nmi request is acknowledged only once ev en if it occurs two times or more). main routine nmi request <1> 1 instruction ex ecution nmi request <2> nmi request <1> execution nmi request <2> pending p ending nmi request <2> processing chapter 14 interrupt functions 273 user? manual u13029ej7v1ud 14.4.2 maskable interrupt request acknowledgement operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt request mask (mk) flag is cleared to 0. a vectored interrupt request is acknowledged in the interrupt enabled status (when the ie flag is set to 1). however, an interrupt request with a lower priority cannot be acknowledged while an interrupt with a higher priority is being serviced (when the isp flag is reset to 0). the time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in table 14-3. for the timing of the interrupt request acknowledgement, refer to figures 14-12 and 14-13 . table 14-3. time from generation of maskable interrupt request to servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note the wait time is the maximum when an interrupt request is generated immediately before a division instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. if the same priorities are specified by the priority specification flag, the interrupt with the highest default priority is acknowledged first. a pending interrupt request is acknowledged when the status in which it can be acknowledged is set. figure 14-11 shows the algorithm of acknowledging interrupt requests. when a maskable interrupt request is acknowledged, the contents are saved to the stack, the program status word (psw) and the program counter (pc), in that order, the ie flag is reset to 0, and the contents of the interrupt priority specification flag of the acknowledged interrupt request are transferred to the isp flag. in addition, the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt servicing, use the reti instruction. 1 f cpu chapter 14 interrupt functions user? manual u13029ej7v1ud 274 figure 14-11. interrupt request acknowledgement program algorithm if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgement of maskable interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = higher priority interrupt servicing, 1 = no interrupt request acknowledged, or lower priority interrupt servicing) start if = 1? no yes (interrupt request generated) mk = 0? yes no interrupt request pending pr = 0? no (low priority) yes (high priority) any interrupt requests of pr = 0 that are generated at same time ? interrupt request pending yes no which interrupt has highest priority of interrupt requests that are generated at same time ? interrupt request pending yes no ie = 1? interrupt request pending no yes isp = 1? interrupt request pending no vectored interrupt servicing interrupt request pending yes no ie = 1? yes interrupt request pending no vectored interrupt servicing yes which interrupt has highest priority of interrupt requests of pr = 0 that are generated at same time ? chapter 14 interrupt functions 275 user? manual u13029ej7v1ud figure 14-12. interrupt request acknowledgement timing (minimum time) remark 1 clock: (f cpu : cpu clock) figure 14-13. interrupt request acknowledgement timing (maximum time) remark 1 clock: (f cpu : cpu clock) 14.4.3 software interrupt request acknowledgement operation the software interrupt request can be acknowledged when the brk instruction is executed. this interrupt cannot be disabled. when the software interrupt request is acknowledged, the contents are saved to the stack, the program status word (psw) and the program counter (pc), in that order, the ie flag is reset to 0, the contents of the vector table (003eh and 003fh) are loaded to the pc, and execution branches. to return from the software interrupt servicing, use the retb instruction. caution do not use the reti instruction to return from the software interrupt. 1 f cpu 1 f cpu instruction instruction saving psw and pc, jumping to interrupt servicing interrupt servicing program cpu processing if pr = 1) 8 clocks if pr = 0) 7 clocks 6 clocks ( ( instruction division instruction saving psw and pc, jumping to interrupt servicing interrupt servicing program cpu processing if pr = 1) 33 clocks if pr = 0) 32 clocks 6 clocks 25 clocks ( ( chapter 14 interrupt functions user? manual u13029ej7v1ud 276 14.4.4 multiple interrupt servicing acknowledging another interrupt request while one interrupt is being serviced is called multiple interrupts. multiple interrupts are not generated unless interrupt requests are enabled (ie = 1) (except the non-maskable interrupt). when an interrupt request is acknowledged, the other interrupts are disabled (ie = 0). to enable multiple interrupts, therefore, the ie flag must be set to 1 by executing the ei instruction during interrupt servicing and interrupts must be enabled. even if interrupt requests are enabled, some multiple interrupts are not acknowledged due to control by the programmable priority. an interrupt has two types of priorities: a default priority and a programmable priority. multiple interrupts are controlled by the programmable priority. in the ei status, if an interrupt request having the same as or higher priority than that of the interrupt currently being serviced is generated, the interrupt is acknowledged as multiple interrupt. if an interrupt request with a priority lower than that of the interrupt currently being serviced is generated, the interrupt is not acknowledged as multiple interrupt. if interrupts are disabled, or if a multiple interrupt is not acknowledged because it has a low priority, the interrupt is held pending. after the servicing of the current interrupt is complete, and after one instruction of the main servicing has been executed, the pending interrupt is acknowledged. multiple interrupts are not acknowledged while the non-maskable interrupt is being serviced. table 14-4 shows interrupt requests enabled for multiple interrupts. figure 14-14 shows multiple interrupt examples. table 14-4. interrupt requests enabled for multiple interrupt during interrupt servicing maskable interrupt request pr = 0 pr = 1 ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt isp = 0 ? isp = 1 ? software interrupt ? remarks 1. : multiple interrupt enabled. : multiple interrupt disabled. 2. isp and ie are flags included in psw. isp = 0: interrupt with higher priority is serviced. isp = 1: interrupt request is not acknowledged or interrupt with lower priority is being serviced. ie = 0: acknowledging interrupt request is disabled. ie = 1: acknowledging interrupt request is enabled. 3. pr is flag included in pr0l, pr0h, and pr1l. pr = 0: higher priority level pr = 1: lower priority level non-maskable interrupt request multiple interrupt request maskable interrupt servicing interrupt chapter 14 interrupt functions 277 user? manual u13029ej7v1ud figure 14-14. multiple interrupt example (1/2) example 1. multiple interrupt is generated twice this multiple interrupt example shows two interrupt requests, intyy and intzz, being acknowledged while interrupt intxx is being serviced. before each interrupt request is acknowledged, the ei instruction is always issued and interrupt requests are enabled. example 2. multiple interrupt is not generated because of its priority intyy, which is generated while intxx is being serviced, is not acknowledged and multiple interrupt servicing is not performed because the priority of intyy is lower than that of intxx. intyy is held pending and is acknowledged after one instruction of the main servicing has been executed. pr = 0: higher priority level pr = 1: lower priority level ie = 0: acknowledging interrupt request is disabled main servicing ei intxx (pr = 1) intyy (pr = 0) ie = 0 ei reti intxx servicing intzz (pr = 0) ie = 0 ei reti intyy servicing ie = 0 reti intzz servicing main servicing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 1) ei ie = 0 ei reti reti chapter 14 interrupt functions user? manual u13029ej7v1ud 278 figure 14-14. multiple interrupt example (2/2) example 3. multiple interrupt is not generated because interrupts not enabled while intxx is serviced, other interrupts are not enabled (the ei instruction has not been executed). therefore, intyy is not acknowledged and multiple interrupt servicing is not performed. this interrupt (intyy) is held pending and is acknowledged after one instruction of the main servicing has been executed. pr = 0: higher priority level ie = 0: acknowledging interrupt request is disabled main servicing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 0) ie = 0 reti reti ei chapter 14 interrupt functions 279 user? manual u13029ej7v1ud 14.4.5 pending interrupt requests there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. these instructions (instructions that have interrupt requests held pending) are listed below. mov psw, #byte mov a, psw mov psw, a mov1 psw. bit, cy mov1 cy, psw. bit and1 cy, psw. bit or1 cy, psw. bit xor1 cy, psw. bit set1 psw. bit clr1 psw. bit retb reti push psw pop psw ? t psw. bit, $addr16 ? f psw. bit, $addr16 btclr psw. bit, $addr16 ?i ?i manipulation instruction to if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, egp, egn, egp5, egn5 registers caution the brk instruction is not one of the above-listed instructions that have interrupt requests held pending. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared to 0. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. however, the non- maskable interrupt request is acknowledged. the timing with which interrupt requests are held pending is shown in figure 14-15. figure 14-15. pending interrupt request remarks 1. instruction n: instruction that has interrupt request held pending 2. instruction m: instruction other than one which has interrupt request held pending 3. the operation of if (interrupt request) is not affected by the value of pr (priority level). instruction m saving psw and pc, jumping to interrupt servicing interrupt servicing program cpu processing if instruction n user? manual u13029ej7v1ud 280 chapter 15 external device expansion function 15.1 external device expansion function the external device expansion function is for connecting an external device to areas other than the internal rom, ram, and sfr areas. to connect an external device, ports 4 and 6 are used. port 4 controls address/data, read/ write strobe, wait, and address strobe signals. the pd780982, 780983, 780984, and 780986 can be expanded with 256 bytes of external memory. by using an external access area in the sfr area, the pd780988 can be expanded with 16 bytes of external memory. caution the external device expansion function can only be used under conditions of f x = 8.38 mhz or lower, and v dd = 4.0 to 5.5 v. table 15-1. pin functions in external memory expansion mode pin function when external device is connected alternate function name function ad0 to ad7 multiplexed address/data bus p40 to p47 rd read strobe signal p64 wr write strobe signal p65 wait wait signal p66 astb address strobe signal p67 table 15-2. status of ports 4 and 6 in external memory expansion mode port port 4 port 6 external expansion mode 0 to 7 4 5 6 7 single-chip mode port port 256-byte memory expansion mode address/data rd, wr, wait, astb caution when the external wait function is not used, the wait pin can be used as a port pin in all the modes. chapter 15 external device expansion function 281 user? manual u13029ej7v1ud the memory map is as follows when the external device expansion function is used. figure 15-1. memory map when external device expansion function used (1/3) (a) memory map of the pd78f0988a when the (b) memory map of the pd78f0988a when pd780982 and flash memory capacity the pd780983 and flash memory are 16 kb capacity are 24 kb 256-byte memory expansion mode (when mem2 to mem0 = 01x) 4100h 40ffh 4000h 3fffh sfr internal high-speed ram reserved single-chip mode ffffh ff00h feffh fb00h faffh 0000h 256-byte memory expansion mode (when mem2 to mem0 = 01x) 6100h 60ffh 6000h 5fffh sfr internal high-speed ram reserved single-chip mode ffffh ff00h feffh fb00h faffh 0000h chapter 15 external device expansion function user? manual u13029ej7v1ud 282 figure 15-1. memory map when external device expansion function used (2/3) (c) memory map of the pd78f0988a when the (d) memory map of the pd78f0988a when pd780984 and flash memory capacity the pd780986 and flash memory are 32 kb capacity are 48 kb sfr internal high-speed ram reserved single-chip mode 256-byte memory expansion mode (when mem2 to mem0 = 01x) ffffh ff00h feffh fb00h faffh 8100h 80ffh 8000h 7fffh 0000h sfr internal high-speed ram internal expansion ram reserved reserved single-chip mode 256-byte memory expansion mode (when mem2 to mem0 = 01x) ffffh ff00h feffh fb00h faffh f800h f7ffh f400h f3ffh c100h c0ffh c000h bfffh 0000h chapter 15 external device expansion function 283 user? manual u13029ej7v1ud figure 15-1. memory map when external device expansion function used (3/3) (e) memory map of the pd78f0988a when the pd780988 and flash memory capacity are 60 kb cautions 1. the pd78f0988a of when the pd780988 and flash memory capacity is 60 kb cannot be expanded with external memory of 256 bytes. use of the sfr area? external access area will allow 16-byte external memory expansion. 2. setting the flash memory capacity to 48 kb or less with the internal memory size switching register (ims) will allow the pd78f0988a to be expanded with 256 bytes of external memory. sfr internal high-speed ram internal expansion ram reserved reserved single-chip mode ffffh ff00h feffh fb00h faffh f800h f7ffh f400h f3ffh f000h efffh 0000h chapter 15 external device expansion function user? manual u13029ej7v1ud 284 15.2 registers controlling external device expansion function the external device expansion function is controlled by the following three registers. memory expansion mode register (mem) memory expansion wait setting register (mm) memory size switching register (ims) (1) memory expansion mode register (mem) mem is a register that sets an external expansion area. mem is set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 15-2. format of memory expansion mode register caution always set bits 3 to 7 to 0. remark : don? care mem 0 symbol 76543210 0 mem2 mem1 mem0 00 0 ff47h address 00h after reset w r/w mem2 0 0 mem1 0 1 mem0 0 single-chip/memory expansion mode selection p40 to p47, p64 to p67 pin status p40 to p47 p64 to p67 port mode ad0 to ad7 p64 = rd p65 = wr p66 = wait p67 = astb other than above setting prohibited single-chip mode 256-byte memory expansion mode chapter 15 external device expansion function 285 user? manual u13029ej7v1ud (2) memory expansion wait setting register (mm) mm is a register that sets the number of wait states. mm is set by an 8-bit memory manipulation instruction. reset input sets this register to 10h. figure 15-3. format of memory expansion wait setting register pw1 pw0 wait state control 00 no wait 01 wait (1 wait state is inserted) 10 setting prohibited 11 wait control by external wait pin caution to perform wait control using the external wait pin, be sure to set the wait/p66 pin to input mode (set bit 6 (pm66) of the port mode register 6 (pm6) to 1). 6543210 7 symbol mm 0 0 pw1 pw0 0 0 0 0 fff8h 10h r/w address after reset r/w chapter 15 external device expansion function user? manual u13029ej7v1ud 286 (3) memory size switching register (ims) this register sets the capacities of the internal rom and internal high-speed ram. ims is set by an 8-bit memory manipulation instruction. reset input sets this register to cfh. figure 15-4. format of memory size switching register note make the flash memory capacity 48 kb or less when using the external device expansion function with the pd78f0988a. cautions 1. the value of ims after reset is the same (cfh) for all the products in the pd780988 subseries, regardless of the internal memory capacity. therefore, be sure to set the value of ims according to the internal memory capacity of the product used. 2. the external memory space can be expanded in a space other than that specified by ims, regardless of the internal memory capacity. table 15-3. set value of internal memory size switching register part number set value of ims pd780982 c4h pd780983 c6h pd780984 c8h pd780986 cch pd780988 cfh note 1 pd78f0988a note 2 notes 1. there is no need to change the set value of ims because the initial value of the pd780988 is cfh. 2. set c4h, c6h, c8h, cch, or cfh according to the mask rom version used. ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ims 76543210 symbol address after reset r/w fff0h cfh r/w rom3 rom2 1 0 1 1 1 1 rom1 rom0 0 0 0 1 0 1 internal rom capacity selection 32 kb 48 kb note 01 0 1 00 1 0 16 kb 24 kb 60 kb setting prohibited other than above ram2 ram1 1 1 ram0 0 internal high-speed ram capacity selection 1,024 bytes setting prohibited other than above chapter 15 external device expansion function 287 user? manual u13029ej7v1ud 15.3 timing of external device expansion function the timing control signal output pins used in the external memory expansion mode are as follows. (1) rd pin (alternate function: p64) this pin outputs a read strobe signal when an instruction is fetched or data is accessed from the external memory. when the internal memory is accessed, the read strobe signal is not output (instead, this pin holds a high level). (2) wr pin (alternate function: p65) this pin outputs a write strobe signal when the external memory is accessed for data. when the internal memory is accessed, the write strobe signal is not output (this pin holds a high level). (3) wait pin (alternate function: p66) this pin inputs an external wait signal. when the external wait signal is not used, the wait pin can be used as an i/o port pin. when the internal memory is accessed, the external wait signal is ignored. (4) astb pin (alternate function: p67) this pin outputs an address strobe signal which is always output regardless of instruction fetch or data access from the external memory. the address strobe signal is also output when the internal memory is accessed. (5) ad0 to ad7 pins (alternate function: p40 to p47) these pins output address and data signals. the valid signals are output or input when instructions are fetched or data is accessed from the external memory. the status of the signal also changes when the internal memory is accessed (the output contents are undefined). figures 15-5 to 15-8 show the timing charts. chapter 15 external device expansion function user? manual u13029ej7v1ud 288 figure 15-5. instruction fetch from external memory (a) when no wait state is set (pw1, pw0 = 0, 0) (b) when wait state is set (pw1, pw0 = 0, 1) (c) when external wait state is set (pw1, pw0 = 1, 1) ad0 to ad7 astb rd address instruction code ad0 to ad7 astb rd address instruction code internal wait signal (1 clock wait) ad0 to ad7 astb rd instruction code wait address chapter 15 external device expansion function 289 user? manual u13029ej7v1ud figure 15-6. read timing of external memory (a) when no wait state is set (pw1, pw0 = 0, 0) (b) when wait state is set (pw1, pw0 = 0, 1) (c) when external wait state is set (pw1, pw0 = 1, 1) ad0 to ad7 astb rd address read data ad0 to ad7 astb rd address read data internal wait signal (1 clock wait) ad0 to ad7 astb rd read data wait address chapter 15 external device expansion function user? manual u13029ej7v1ud 290 figure 15-7. write timing of external memory (a) when no wait state is set (pw1, pw0 = 0, 0) (b) when wait state is set (pw1, pw0 = 0, 1) (c) when external wait state is set (pw1, pw0 = 1, 1) ad0 to ad7 astb wr address write data hi-z ad0 to ad7 astb wr address write data hi-z internal wait signal (1 clock wait) ad0 to ad7 astb wr write data hi-z wait address chapter 15 external device expansion function 291 user? manual u13029ej7v1ud figure 15-8. read-modify-write timing of external memory (a) when no wait state is set (pw1, pw0 = 0, 0) (b) when wait state is set (pw1, pw0 = 0, 1) (c) when external wait state is set (pw1, pw0 = 1, 1) astb ad0 to ad7 read data write data rd address wr hi-z astb ad0 to ad7 read data write data rd address wr internal wait signal (1 clock wait) hi-z wait astb ad0 to ad7 read data write data rd wr hi-z address chapter 15 external device expansion function user? manual u13029ej7v1ud 292 15.4 example of connection with memory figure 15-9 shows an example of connecting the pd780984 and an external memory. in this application example, sram is connected. in addition, the external device expansion function is used in the full address mode, and 32 kb of addresses, 0000h to 7fffh, are allocated to internal rom; addresses 8000h and higher are allocated to sram. figure 15-9. example of connecting pd780984 and memory rd ad0 to ad7 wr astb d0 to d7 le oe q0 to q7 v dd address bus a0 to a7 we oe cs i/o1 to i/o8 data bus pd780984 74hc573 pd43256b 293 user? manual u13029ej7v1ud chapter 16 standby function 16.1 standby function and configuration 16.1.1 standby function the standby function is used to reduce the current consumption of the system and can be effected in the following two modes. (1) halt mode this mode is set when the halt instruction is executed. the halt mode stops the operation clock of the cpu. the system clock oscillator continues oscillating. this mode does not reduce the current consumption as much as the stop mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations such as a watch operation. (2) stop mode this mode is set when the stop instruction is executed. the stop mode stops the system clock oscillator and stops the entire system. the current consumption of the cpu can be substantially reduced in this mode. the low voltage (v dd = 2.0 v) of the data memory can be retained. therefore, this mode is useful for retaining the contents of the data memory at an extremely low current. the stop mode can be released by an interrupt request, so this mode can be used for intermittent operation. however, a certain amount of time is required until the system clock oscillator stabilizes after the stop mode is released. if processing must be resumed immediately by using an interrupt request, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all retained. in addition, the statuses of the output latch of the i/o ports and output buffer are also retained. cautions 1. to set the stop mode, be sure to stop the operations of the peripheral hardware before executing the stop instruction. 2. to reduce the current consumption of the a/d converter, clear bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0 to stop a/d conversion, and then execute the halt or stop instruction. chapter 16 standby function user? manual u13029ej7v1ud 294 16.1.2 register controlling standby function the wait time during which oscillation is stabilized after the stop mode is released by an interrupt request is controlled by the oscillation stabilization time select register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets this register to 04h. therefore, to release the stop mode by inputting the reset signal, the time required to release the mode is 2 17 /f x . figure 16-1. format of oscillation stabilization time select register note expanded-specification products only. caution the wait time when the stop mode is released does not include the time required for the clock oscillation to start after the stop mode has been released (see ??in the figure below). the same applies when the stop mode is released by reset input or generation of an interrupt request. remark f x : system clock oscillation frequency v ss1 stop mode released voltage waveform of x1 pin a 6543210 7 symbol osts 0 0 0 0 0 osts2 osts1 osts0 fffah 04h r/w address after reset r/w osts2 0 0 0 osts1 0 0 1 01 10 other than above selects oscillation stabilization tim when stop mode released 2 12 /f x 2 14 /f x 2 15 /f x osts0 0 1 0 2 16 /f x 1 2 17 /f x setting prohibited 0 341.3 s 1.36 ms 2.73 ms 5.46 ms 10.9 ms 488.8 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms at f x = 12 mhz note at f x = 8.38 mhz chapter 16 standby function 295 user? manual u13029ej7v1ud 16.2 operation of standby function 16.2.1 halt mode (1) setting and operation status of halt mode the halt mode is set by executing the halt instruction. the operation status in the halt mode is shown in the table below. table 16-1. operation status in halt mode clock generator oscillatable supply of clock to cpu is stopped. cpu stops operation. port (output latch) retains previous status before setting halt mode. 16-bit timer/event counter operable 8-bit timer/event counter 10-bit inverter control timer watchdog timer real-time output port a/d converter serial interface external interrupt externally ad0 to ad7 high impedance extended bus line astb low level wr, rd high level wait high impedance item operation status chapter 16 standby function user? manual u13029ej7v1ud 296 (2) releasing halt mode the halt mode can be released by the following three sources. (a) releasing by unmasked interrupt request if an unmasked interrupt request is generated, the halt mode is released. if the interrupt request is enabled at this time, vectored interrupt servicing is performed. if the interrupt request is disabled, the instruction at the next address is executed. figure 16-2. releasing halt mode by interrupt request remarks 1. the dotted lines indicate the case when the interrupt request that has released the standby mode is acknowledged. 2. the wait time is as follows. when vectored interrupt servicing is performed: 8 to 9 clocks when vectored interrupt servicing is not performed: 2 to 3 clocks (b) releasing by non-maskable interrupt request if a non-maskable interrupt request is generated, the halt mode is released regardless of whether interrupt requests are enabled or disabled, and vectored interrupt servicing is performed. halt instruction standby release signal wait wait halt mode operation mode operation mode clock oscillation interrupt request chapter 16 standby function 297 user? manual u13029ej7v1ud (c) releasing by reset input if the reset signal is input, the halt mode is released. after branching to the reset vector address in the same manner as the ordinary reset operation, and program execution is started again. figure 16-3. releasing halt mode by reset input remarks 1. f x : system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 12 mhz. table 16-2. operation after release of halt mode releasing source mk pr ie isp operation maskable interrupt request 0 0 0 executes next address instruction. 001 executes interrupt servicing. 01 01 executes next address instruction. 01 0 01 11 executes interrupt servicing. 1 retains halt mode. non-maskable interrupt request executes interrupt servicing. reset input executes reset processing. : don? care halt instruction reset signal wait (2 17 /f x : 10.9 ms) reset period halt mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation chapter 16 standby function user? manual u13029ej7v1ud 298 16.2.2 stop mode (1) setting and operation status of stop mode the stop mode is set by executing the stop instruction. cautions 1. when the stop mode is set, the x2 pin is internally pulled up to v dd1 to suppress the current leakage of the crystal oscillator block. therefore, do not use the stop mode in a system where the external clock is used as the system clock. 2. because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. when the stop mode is set, therefore, the halt mode is set immediately after the stop instruction has been executed, the wait time set by the oscillation stabilization time select register (osts) elapses, and then an operation mode is set. the following table shows the operation status in the stop mode. table 16-3. operation status in stop mode clock generator oscillation stopped. cpu stops operation. output port (output latch) retains previous status immediately before stop instruction execution. 16-bit timer/event counter operable only when ti000 or ti001 is selected as count clock. 8-bit timer/event counter operable only when ti50, ti51, or ti52 is selected as count clock. 10-bit inverter control timer stops operation. watchdog timer stops operation. real-time output port operable when external trigger is used or when ti010, ti011, or ti52 is selected as count clock of timer/event counter. a/d converter stops operation. serial interface stops operation. external interrupt operable ad0 to ad7 high impedance astb low level wr, rd high level wait high impedance operation status item externally extended bus line chapter 16 standby function 299 user? manual u13029ej7v1ud (2) releasing stop mode the stop mode can be released by the following two sources. (a) releasing by unmasked interrupt request if an unmasked interrupt request is generated, the stop mode can be released. if interrupt requests are enabled at this time, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed. if interrupt requests are in the acknowledgement disabled status, the instruction at the next address is executed. figure 16-4. releasing stop mode by interrupt request remark the dotted lines indicate the case when the interrupt request that has released the standby mode is acknowledged. stop instruction standby release signal wait (set time by osts) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation interrupt request chapter 16 standby function user? manual u13029ej7v1ud 300 (b) releasing by reset input if the reset signal is input, the stop mode is released. the reset operation is performed after the oscillation stabilization time has elapsed. figure 16-5. releasing stop mode by reset input remarks 1. f x : system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 12 mhz. table 16-4. operation after release of stop mode releasing source mk pr ie isp operation maskable interrupt request 0 0 0 executes next address instruction. 001 executes interrupt servicing. 01 01 executes next address instruction. 01 0 01 11 executes interrupt servicing. 1 retains stop mode. reset input executes reset processing. : don? care stop instruction reset signal wait (2 17 /f x : 10.9 ms) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation reset period 301 user? manual u13029ej7v1ud chapter 17 reset function the reset signal can be effected by the following two methods. (1) external reset input from reset pin (2) internal reset by inadvertent program loop detection by watchdog timer there is no functional difference between the external reset and internal reset, and execution of the program is started from addresses written to addresses 0000h and 0001h when the reset signal is input. the reset function is effected when a low-level signal is input to the reset pin or when an overflow occurs in the watchdog timer. as a result, each hardware enters the status shown in table 17-1. each pin goes into a high- impedance state while the reset signal is input, and during the oscillation stabilization time immediately after the reset function has been released. when a high-level signal is input to the reset pin, the reset function is released, and program execution is started after oscillation stabilization time (2 17 /f x ) has elapsed. the reset function effected by an overflow in the watchdog timer is automatically released after reset, and program execution is started after the oscillation stabilization time (2 17 / f x ) has elapsed (refer to figures 17-2 to 17-4 ). cautions 1. input a low-level signal to the reset pin for 10 s or longer to execute an external reset. 2. oscillation of the system clock is stopped while the reset signal is being input. 3. when releasing the stop mode by the reset input, the contents during the stop mode are retained while the reset signal is being input. however, the port pins go into a high- impedance state. figure 17-1. reset function block diagram reset controller watchdog timer reset count clock stop overflow reset signal interrupt function chapter 17 reset function user? manual u13029ej7v1ud 302 figure 17-2. reset timing by reset input figure 17-3. reset timing by overflow in watchdog timer figure 17-4. reset timing by reset input in stop mode reset internal reset signal port pin x1 delay delay during normal operation reset period (oscillation stopped) oscillation stabilization time wait normal operation (reset processing) hi-z overflow in watchdog timer internal reset signal port pin x1 during normal operation reset period (oscillation stopped) oscillation stabilization time wait normal operation (reset processing) hi-z reset internal reset signal port pin x1 delay delay during normal operation oscillation stabilization time wait normal operation (reset processing) hi-z stop status (oscillation stopped) reset period (oscillation stopped) stop instruction execution chapter 17 reset function 303 user? manual u13029ej7v1ud table 17-1. status of each hardware after reset (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) are set stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general-purpose registers undefined note 2 port (output latch) ports 0 to 6 (p0 to p6) 00h port mode registers (pm0, pm2 to pm6) ffh pull-up resistor option registers (pu0, pu2 to pu6) 00h processor clock control register (pcc) 04h memory expansion mode register (mem) 00h memory expansion wait setting register (mm) 10h internal memory size select register (ims) cfh note 3 internal expansion ram size select register (ixs) 0ch note 4 flash programming mode control register (flpmc) 08h note 5 oscillation stabilization time select register (osts) 04h real-time output port mode registers (rtpm00, rtpm01) 00h control registers (rtpc00, rtpc01) 00h dc control registers (dcctl0, dcctl1) 00h buffer registers (rtbl00, rtbh00, rtbl01, rtbh01) 00h notes 1. only the contents of the pc among hardware become undefined during reset input and oscillation stabilization time wait. the other statuses do not differ from those after reset. 2. if the reset signal is input in the standby mode, the status before reset is retained even after reset. 3. set the following value before operating each device even though the initial value is cfh. pd780982: c4h pd780983: c6h pd780984: c8h pd780986: cch pd780988: cfh (no need to change the set value of ims because the initial ims value of the pd780988 is cfh). pd78f0988a:values corresponding to those of mask rom versions 4. set the following value before operating each device even though the initial value is 0ch. pd780982, 780983, 780984: 0ch (no need to change the set value of ixs because the initial ixs value of the pd780982, 780983, 780984 are set to 0ch). pd780986, 780988: 0ah pd78f0988a: values corresponding to those of mask rom versions 5. bit 2 changes according to v pp voltage level. chapter 17 reset function user? manual u13029ej7v1ud 304 table 17-1. status of each hardware after reset (2/2) hardware status after reset 10-bit inverter control timer compare registers (cm0 to cm2) 0000h compare register (cm3) 00ffh buffer registers (bfcm0 to bfcm2) 0000h buffer register (bfcm3) 00ffh dead-time reload register (dtime) ffh control register (tmc7) 00h mode register (tmm7) 00h 16-bit timer/event counter timer counters (tm00, tm01) 0000h capture/compare control registers (crc00, crc01) 00h capture/compare registers (cr000, cr010, cr001, undefined cr011) prescaler mode registers (prm00, prm01) 00h mode control registers (tmc00, tmc01) 00h timer output control registers (toc00, toc01) 00h 8-bit timer/event counter timer counters (tm50 to tm52) 00h compare registers (cr50 to cr52) undefined clock select registers (tcl50 to tcl52) 00h mode control registers (tmc50 to tmc52) 00h watchdog timer clock select register (wdcs) 00h mode register (wdtm) 00h serial interface asynchronous serial interface mode registers 00h (asim00, asim01) asynchronous serial interface status registers 00h (asis00, asis01) transmit shift registers (txs00, txs01) ffh receive buffer registers (rxb00, rxb01) ffh baud rate generator control registers 00h (brgc00, brgc01) shift register (sio3) undefined mode register (csim3) 00h a/d converter mode register (adm0) 00h conversion result register (adcr0) undefined analog input channel specification register (ads0) 00h interrupt request flag registers (if0l, if0h, if1l) 00h mask flag registers (mk0l, mk0h, mk1l) ffh priority specification flag registers (pr0l, pr0h, pr1l) ffh external interrupt rising edge enable registers (egp, egp5) 00h external interrupt falling edge enable registers (egn, egn5) 00h 305 user? manual u13029ej7v1ud chapter 18 pd78f0988a the pd78f0988a replaces the on-chip mask rom of the pd780988 with flash memory, which can be written, deleted, and rewritten while mounted on the board. table 18-1 lists the differences between the pd78f0988a and the mask rom versions. table 18-1. differences between pd78f0988a and mask rom versions item pd78f0988a mask rom versions internal rom type flash memory mask rom internal rom capacity 60 kb note 1 pd780982: 16 kb pd780983: 24 kb pd780984: 32 kb pd780986: 48 kb pd780988: 60 kb internal expansion ram capacity 1,024 bytes note 2 pd780982, 780983, 780984: none pd780986, 780988: 1,024 bytes test pin not available available v pp pin available not available notes 1. by using the internal memory size switching register (ims), the flash memory capacity can be set to the same capacity as the memory in the mask rom versions. 2. by using the internal expansion ram size switching register (ixs), the flash memory capacity can be set to the same capacity as the memory in the mask rom versions. caution there are differences in noise immunity and noise radiation between the flash memory versions and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom versions. chapter 18 pd78f0988a user? manual u13029ej7v1ud 306 18.1 internal memory size switching register for the pd78f0988a, it is possible to select the capacity of the internal memory using the internal memory size switching register (ims). by setting ims, the internal memory of the pd78f0988 can be mapped identically to that of a mask rom version. ims is set by an 8-bit memory manipulation instruction. reset input sets this register to cfh. figure 18-1. format of memory size switching register the values set to ims in order to obtain the same memory map as mask rom versions are shown in table 18-2. table 18-2. set values of memory size switching register applicable mask rom versions set value of ims pd780982 c4h pd780983 c6h pd780984 c8h pd780986 cch pd780988 cfh caution when mask rom versions are used, ims should be set to the values shown in table 18-2. the setting value for the pd780988 is cfh, so it is not necessary to change the initial value. ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ims 76543210 symbol address after reset r/w fff0h cfh r/w rom3 rom2 1 0 1 1 1 1 rom1 rom0 0 0 0 1 0 1 internal rom capacity selection 32 kb 48 kb 0 1 0 1 0 0 1 0 16 kb 24 kb 60 kb setting prohibited other than above ram2 ram1 1 1 ram0 0 internal high-speed ram capacity selection 1024 bytes setting prohibited other than above chapter 18 pd78f0988a 307 user? manual u13029ej7v1ud 18.2 internal expansion ram size switching register for the pd78f0988a, it is possible to select the capacity of the internal expansion ram using the internal expansion ram size switching register (ixs). by setting ixs, the same memory map as mask rom versions with different internal expansion ram capacities is possible. ixs is set by an 8-bit memory manipulation instruction. reset input sets this register to 0ch. figure 18-2. format of internal expansion ram size switching register the values set to ixs in order to obtain the same memory map as mask rom versions are shown in table 18-3. table 18-3. set values of internal expansion ram size switching register applicable mask rom versions set value of ixs pd780982 0ch pd780983 pd780984 pd780986 0ah pd780988 caution when mask rom versions are used, ixs should be set to the values shown in table 18-3. the setting value for the pd780982, 780983, and 780984 is 0ch, so it is not necessary to change the initial value. 0 0 0 ixram4 ixram3 ixram2 ixram1 ixram0 ixs 76543210 symbol address after reset r/w fff4h 0ch r/w ixram4 ixram3 0 1 0 1 ixram2 ixram1 ixram0 0 1 1 0 0 0 internal expansion ram capacity selection 1024 bytes no internal expansion ram setting prohibited other than above chapter 18 pd78f0988a user? manual u13029ej7v1ud 308 18.3 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the pd78f0988a mounted (on- board). a flash memory writing adapter (program adapter), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are the products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). write or erase the flash memory under the following conditions. ? expanded-specification products 4.5 v v dd 5.5 v: f x = 10.0 mhz or lower 3.0 v v dd < 4.5 v: f x = 8.38 mhz or lower ? conventional products 4.0 v v dd 5.5 v: f x = 8.38 mhz or lower refer to chapter 20 electrical specifications (expanded-specification products) and chapter 21 electrical specifications (conventional products) for details of conditions other than the above. programming using flash memory has the following advantages. ? software can be modified after the microcontroller is solder-mounted on the target system. ? distinguishing software facilities low-quantity, varied model production ? easy data adjustment when starting mass production 18.3.1 programming environment the following shows the environment required for pd78f0988a flash memory programming. when flashpro iii or flashpro iv is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals for flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 18-3. environment for writing program to flash memory host machine rs-232c usb dedicated flash programmer pd78f0988a v pp v dd v ss reset sio/uart/port chapter 18 pd78f0988a 309 user? manual u13029ej7v1ud 18.3.2 communication mode use the communication mode shown in table 18-4 to perform communication between the dedicated flash programmer and pd78f0988a. table 18-4. communication mode list communication type setting note 1 pins used number of v pp mode comm port sio clock cpu clock flash clock multiple rate pulses 3-wire serial i/o sio ch-0 100 hz to any 1 to 10 mhz 1.0 si/p52 0 (sio3) (3-wired, 1.25 mhz note 2 so/p53 sync.) note 2 sck/p51 3-wire serial i/o sio ch-3 si/p52 3 (sio3) with + handshake so/p53 handshake sck/p51 p50 (hs) uart uart ch-0 4,800 to any 1 to 10 mhz 1.0 rxd00/p20 8 (uart00) (async.) 76,800 bps note 2 txd00/p21 notes 2, 4 pseudo 3-wire port a 100 hz to 1 any 1 to 10 mhz 1.0 p24/ti50/to50 12 serial i/o note 3 (pseudo- khz note 2 note 2 (serial data input) 3-wired) p25/ti51/to51 (serial data output) p26/ti52/to52 (serial clock input) notes 1. selection items for type settings on the dedicated flash programmer (flashpro iii/flashpro iv). 2. the possible setting range differs depending on the voltage. for details, refer to chapter 20 electrical specifications (expanded-specification products) and chapter 21 electrical specifications (conventional products) . 3. serial transfer is executed by controlling the port with software. 4. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. figure 18-4. communication mode selection format 10 v v pp v pp pulses flash memory write mode reset v dd v ss v dd v ss chapter 18 pd78f0988a user? manual u13029ej7v1ud 310 figure 18-5. example of connection with dedicated flash programmer (1/2) (a) 3-wire serial i/o (sio3) dedicated flash programmer vpp1 vdd reset sck so si clk note gnd v pp v dd0 , v dd1 , av dd reset sck si so x1 v ss0 , v ss1 , av ss , av ref pd78f0988a (b) 3-wire serial i/o (sio3) with handshake dedicated flash programmer vpp1 vdd reset sck so si hs gnd v pp v dd0 , v dd1 , av dd reset sck si so p50 (hs) clk note x1 v ss0 , v ss1 , av ss , av ref pd78f0988a (c) uart (uart00) dedicated flash programmer vpp1 vdd reset so (t x d) si (r x d) clk note gnd v pp v dd0 , v dd1 , av dd reset r x d00 t x d00 x1 v ss0 , v ss1 , av ss , av ref pd78f0988a note connect this pin when the system clock is supplied from the dedicated flash programmer. if a resonator is already connected to the x1 pin, the clk pin does not need to be connected. caution the v dd0 and v dd1 pins, if already connected to the power supply, must be connected to the vdd pin of the dedicated flash programmer. before using the power supply connected to the v dd0 and v dd1 pins, supply voltage before starting programming. chapter 18 pd78f0988a 311 user? manual u13029ej7v1ud figure 18-5. example of connection with dedicated flash programmer (2/2) (d) pseudo 3-wire serial i/o note connect this pin when the system clock is supplied from the dedicated flash programmer. if a resonator is already connected to the x1 pin, the clk pin does not need to be connected. caution the v dd0 and v dd1 pins, if already connected to the power supply, must be connected to the vdd pin of the dedicated flash programmer. before using the power supply connected to the v dd0 and v dd1 pins, supply voltage before starting programming. if flashpro iii/flashpro iv is used as a dedicated flash programmer, the following signals are generated for the pd78f0988a. for details, refer to the manual of flashpro iii/flashpro iv. table 18-5. pin connection list signal name i/o pin function pin name sio3 sio3 (hs) uart00 pseudo 3-wired vpp1 output write voltage v pp vpp2 ?? ? vdd i/o v dd voltage generation/ v dd0 , v dd1 , av dd note note note note voltage monitoring gnd ? ground v ss0 , v ss1 , av ss , av ref clk output clock output x1 reset output reset signal reset si (rxd) input reception signal so/txd00/p25 so (txd) output transmit signal si/rxd00/p24 sck output transfer clock sck/p26 hs input handshake signal p50 (hs) note v dd voltage must be supplied before programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin need not be connected. : pin need not be connected. dedicated flash programmer vpp1 vdd reset sck so si clk note gnd v pp v dd0 , v dd1 , av dd reset p26 (serial clock input) p24 (serial data input) p25 (serial data output) x1 v ss0 , v ss1 , av ss , av ref pd78f0988a chapter 18 pd78f0988a user? manual u13029ej7v1ud 312 18.3.3 on-board pin processing when performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. an on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. chapter 18 pd78f0988a 313 user? manual u13029ej7v1ud (1) signal conflict if the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this, isolate the connection with the other device or set the other device to the output high impedance status. figure 18-7. signal conflict (input pin of serial interface) input pin signal conflict connection pin of dedicated flash programmer other device output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device. pd78f0988a (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. to prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. figure 18-8. abnormal operation of other device pin connection pin of dedicated flash programmer other device input pin if the signal output by the pd78f0988a affects another device in the flash memory programming mode, isolate the signals of the other device. pin connection pin of dedicated flash programmer other device input pin if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. pd78f0988a pd78f0988a chapter 18 pd78f0988a user? manual u13029ej7v1ud 314 chapter 18 pd78f0988a 315 user? manual u13029ej7v1ud 18.3.4 connection of adapter for flash writing the following figures show the examples of recommended connection when the adapter for flash writing is used. figure 18-10. wiring example for flash writing adapter with 3-wire serial i/o (sio3) (a) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14) pd78f0988a gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (3.0 to 5.5 v: expanded-specification products) (4.0 to 5.5 v: conventional products) chapter 18 pd78f0988a user? manual u13029ej7v1ud 316 (b) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pd78f0988a vdd2 (lvdd) vdd gnd si so sck clkout reset vpp writer interface reserve/hs frash gnd vdd (3.0 to 5.5 v: expanded-specification products) (4.0 to 5.5 v: conventional products) chapter 18 pd78f0988a 317 user? manual u13029ej7v1ud figure 18-11. wiring example for flash writing adapter with 3-wire serial i/o (sio3) with handshake (a) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14) pd78f0988a gnd vdd si so sck clkout reset vpp reserve/hs writer interface gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vdd2 (lvdd) vdd (3.0 to 5.5 v: expanded-specification products) (4.0 to 5.5 v: conventional products) chapter 18 pd78f0988a user? manual u13029ej7v1ud 318 (b) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pd78f0988a vdd gnd si so sck clkout reset vpp writer interface reserve/hs frash gnd vdd vdd2 (lvdd) (3.0 to 5.5 v: expanded-specification products) (4.0 to 5.5 v: conventional products) chapter 18 pd78f0988a 319 user? manual u13029ej7v1ud figure 18-12. wiring example for flash writing adapter with uart (uart00) (a) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14) pd78f0988a gnd vdd si so sck clkout reset vpp reserve/hs writer interface gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vdd2 (lvdd) vdd (3.0 to 5.5 v: expanded-specification products) (4.0 to 5.5 v: conventional products) chapter 18 pd78f0988a user? manual u13029ej7v1ud 320 (b) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pd78f0988a vdd gnd si so sck clkout reset vpp writer interface reserve/hs frash gnd vdd vdd2 (lvdd) (3.0 to 5.5 v: expanded-specification products) (4.0 to 5.5 v: conventional products) chapter 18 pd78f0988a 321 user? manual u13029ej7v1ud figure 18-13. wiring example for flash writing adapter with pseudo 3-wire serial i/o (a) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14) pd78f0988a gnd vdd si so sck clkout reset vpp reserve/hs writer interface gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vdd2 (lvdd) vdd (3.0 to 5.5 v: expanded-specification products) (4.0 to 5.5 v: conventional products) chapter 18 pd78f0988a user? manual u13029ej7v1ud 322 (b) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pd78f0988a vdd gnd si so sck clkout reset vpp writer interface reserve/hs frash gnd vdd vdd2 (lvdd) (3.0 to 5.5 v: expanded-specification products) (4.0 to 5.5 v: conventional products) chapter 18 pd78f0988a 323 user? manual u13029ej7v1ud 18.4 flash memory programming by self write with the pd78f0988a, it is possible to rewrite the flash memory by a program. 18.4.1 flash memory configuration the configuration of the flash memory is shown in figure 18-14. figure 18-14. flash memory configuration normal operation mode self-write mode flash memory flpmc 01h flpmc 00h erase area (fixed) (52 kb) boot area (fixed) (8 kb) boot area (8 kb) erase/write routine call erase/ write erase area (52 kb) firmware area (with erase/write routine) (7 kb) rom flash memory efffh 2000h 1fffh 0000h efffh 2000h 1fffh 9bffh 8000h 0000h * this area cannot be accessed with a normal instruction. chapter 18 pd78f0988a user? manual u13029ej7v1ud 324 18.4.2 flash programming mode control register the flash programming mode control register (flpmc) is a register for checking the operation mode selection and v pp pin status. flpmc is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 08h. figure 18-15. format of flash programming mode control register notes 1. bit 2 changes depending on the level of v pp . 2. bit 2 is read only. cautions 1. the vpp bit indicates the status of the voltage applied to the v pp pin. if the vpp bit is 0, the voltage required for erase/write is not being applied. however, even if the vpp bit is 1, it does not necessarily mean that the voltage required for erase/write is being applied. set the hardware so that the voltage required for erase/write is applied to the v pp pin. also, if using software in addition to hardware to check that the voltage required for erase/ write is being applied, use an external hardware detection circuit and its output. 2. the initial values of bits 1 and 3 to 7 should not be changed. 18.4.3 self-write procedure the procedure for performing self write is shown below (see figure 18-16 ). (1) disable interrupts. (2) designate the self-write mode (flpmc = 09h). (3) select register bank 3. (4) specify the start address of the entry ram for the hl register. (5) v pp : on (on signal for voltage ic) (6) check the v pp level. (7) initialize the flash subroutine. (8) set the parameters. (9) control the flash memory (erase, write, etc.). (10) v pp : off (off signal for voltage ic) (11) designate the normal operating mode (flpmc = 08h). 0 000 vpp0 flspm0 flpmc vpp v pp pin voltage status 0 1 the voltage required for erase/write is not applied to v pp pin. voltage greater than that of v dd pin is applied to v pp pin. flspm0 operation mode selection 0 1 normal operation mode self-write mode ff89h 08h note 1 r/w note 2 54 symbol address after reset r/w 1 76 32 0 1 chapter 18 pd78f0988a 325 user? manual u13029ej7v1ud figure 18-16. self programming flowchart (1/2) note differs depending on the user program. remark for <1> to <4>, refer to the following flowchart. disable interrupts select register bank 3 specify the entry ram address initialize the flash subroutine set the parameters pre-write erase error? write data verify v pp : off (10) (9) (8) (7) (6) (5) (1) (2) (3) (4) (11) designate normal operating mode (flpmc = 08h) bank error? number of errors? flash memory error v pp : on v pp = 1? no yes no no yes nth time note less than n times note error? no yes yes designate the self-write mode (flpmc = 09h) <1> <2> <3> <4> chapter 18 pd78f0988a user? manual u13029ej7v1ud 326 figure 18-16. self programming flowchart (2/2) <1> <2> <3> <4> overerase error ? overerase error ? blank error ? number of specified erases finished? number of specified retries finished? write back ? yes (error) yes (error) yes (end) yes (end) no (normal) no (normal) no (normal) no (continue) no (continue) yes (error) chapter 18 pd78f0988a 327 user? manual u13029ej7v1ud figure 18-17. self-write timing v dd v pp reset cpu operation and program processing reset mode reset mode normal operation mode flpmc 09h v pp : on writing to flash memory v pp = 10 v 0.3 v v pp : off flpmc 08h normal operation mode self-write mode normal program processing normal program processing mode setting erase write verify mode setting 5 v 0 v 10 v 0 v 5 v 0 v 4.5 v 9.7 v 0.2v dd 0.2v dd 0.2v dd 4.5 v chapter 18 pd78f0988a user? manual u13029ej7v1ud 328 18.4.4 cpu resources the cpu resources used during self write are as follows. register bank: bank3 (8 bytes) b register: status flag c register: function number hl register: entry ram area starting address stack area: maximum 16 bytes write data storage area: 1 to 256 bytes entry ram area: 32 bytes ram area used by the self-write subroutines. can be specified by the user using the hl register. status flag 76543210 parameter verify error write error erase error blank check setting error error 18.4.5 entry ram area a description of the entry ram area is shown in table 18-6. table 18-6. entry ram area offset value description +0 reserved area (1 byte) +1 reserved area (1 byte) +2 and +3 flash memory start address (2 bytes) +4 and +5 reserved area (2 bytes) +6 no. of bytes written in flash memory (1 byte) +7 write time data (1 byte) +8 to +10 erase time data (3 bytes) +11 to +13 writeback time data (3 bytes) +14 and +15 write data storage buffer starting address (2 bytes) +16 and +17 total number of blocks and areas (2 bytes) +18 reserved area (15 bytes) : . example when the value of the hl register of register bank 3 is 0fd00h 0fd00h: status 0fd02h: flash memory start address 0fd06h: number of bytes written in flash memory chapter 18 pd78f0988a 329 user? manual u13029ej7v1ud the entry ram area is explained in detail below. (a) flash memory start address this is the flash memory address value used by the _flashbytewrite subroutine. (b) number of bytes written in flash memory area number and number of bytes written in the flash memory. (c) write time data set the following values according to the operating frequency. f x (mhz) setting value 1.00 to 1.28 20h 1.29 to 2.56 40h 2.57 to 5.12 60h 5.13 to 8.38 80h 8.39 to 10.0 a0h (d) erase time data setting value = erase time (s) operating frequency/2 9 + 1 (erase time range: 0.2 to 20 seconds, up to 100 times in 20 seconds are possible, assuming that one erase time is 0.2 seconds) example erase time: 0.2 seconds, operating frequency: 5 mhz setting value = 0.2 5,000,000/512 + 1 = 1954 (decimal) = 7a2 (hexadecimal) (e) write data storage buffer starting address this area contains the starting address of the write data storage buffer area. the ram data (write data) specified by the address data in this area is written in the flash memory (_flashbytewrite subroutine). the data in this area is specified as the starting address and it is possible to specify up to a maximum of 256 bytes of write data. (f) writeback time setting value = writeback time (s) operating frequency/2 7 (up to 30 times in 1.5 seconds are possible, assuming that one writeback time is 0.05 seconds.) example writeback time: 0.05 seconds, operating frequency: 5 mhz setting value = 0.05 5,000,000/128 = 1953 (decimal) = 7a1 (hexadecimal) chapter 18 pd78f0988a user? manual u13029ej7v1ud 330 18.4.6 self-write subroutines the self-write subroutines and their functions are shown in table 18-7 below. table 18-7. list of self-write subroutines function number subroutine name function decimal hexadecimal 0 00h _flashenv initializes the flash subroutine. 1 01h _flashsetenv sets the parameters. 2 02h _flashgetinfo reads flash information. 16 10h _flashareablankcheck performs a blank check of a specified area. 32 20h _flashareaprewrite performs prewrite for a specified area. 48 30h _flashareaerase erases a specified area. 54 40h _flashareawriteback writes back to a specified area. 80 50h _flashbytewrite writes continuously in byte units. 96 60h _flashareaiverify performs internal verification of a specified area. chapter 18 pd78f0988a 331 user? manual u13029ej7v1ud (1) _flashenv subroutine [function] initializes the flash subroutine. [argument] entry ram address ...... 2 bytes (hl register) [return value] none [register/memory status after called] entry ram address [call example] when the entry ram address = 0fc30h di set1 flspm0 loop: bf vpp, $loop sel rb3 movw hl, #0fc30h ; entry ram address ; * * * * * * * * * * initialization * * * * * * * * * * mov c, #0h ; flashenv (function number setting) call !8100h . . . [flowchart] _flashenv clear entry ram. set the write time setting parameter to the default value. set the erase time setting parameter to the default value. normal end 0.2 s 50 s function number = 0h chapter 18 pd78f0988a user? manual u13029ej7v1ud 332 (2) _flashsetenv subroutine [function] sets the parameters. [argument] write time data: 1 byte (offset value: +7) erase time data: 3 bytes (offset value: +8 to 10) [return value] status (b register) 00h: normal end 80h: parameter setting error [register/memory status after called] entry ram address, write time data, erase time data [call example] when the entry ram address = 0fc30h mov a, #20h ; write time data mov !0fc37h, a mov a, #a2h ; erase time data mov !0fc38h, a ; 0.2 s : 0007a2h (at 5 mhz) mov a, #07h mov !0fc39h, a mov a, #00h mov !0fc3ah, a mov a, #0a1h ; writeback time data setting mov !0fc3bh, a ; 50 ms : 0007a1h (at 5 mhz) mov a, #07h mov !0fc3ch, a mov a, #00h mov !0fc3dh, a mov a, #02h mov !0fc40h, a ; total block number data setting mov !0fc41h, a ; total area number data setting ; mov c, #1h ; flashsetenv (function number setting) call !8100h chapter 18 pd78f0988a 333 user? manual u13029ej7v1ud [flowchart] _flashsetenv check the parameter range of the write time setting. check the parameter range of the erase time setting. normal end parameter setting error no error no error error error function number = 1h check the parameter range of the writeback time setting. no error error normal end chapter 18 pd78f0988a user? manual u13029ej7v1ud 334 (3) _flashgetinfo subroutine [function] reads the flash product identification codes. ? pd78f0988a signature: 50h ? pd78f0988 (old product) signature: 40h [argument] flash product identification code: 1 byte (offset value: +6) [return value] status (b register) 00h: normal end 80h: option specify error product identification code (a register) [register/memory status after called] entry ram starting address [call example] when the entry ram address = 0fc30h mov a, #0h mov !0fc36h, a ; mov c, #40h ; flashgetinfo (function number setting) call !8100h [note] this function enables new products to be distinguished from old products. chapter 18 pd78f0988a 335 user? manual u13029ej7v1ud _flashareablankcheck function number = 10h error error no error no error area check blank check overerase check normal end blank check error overerase check error area number specification error (4) _flashareablankcheck subroutine [function] performs a blank check of a specified area. [argument] area number (= 0, 1): 1 byte (offset value: +6) 0: blank check of area 0000h to 1fffh (boot area) 1: blank check of area 2000h to efffh [return value] status (b register) 00h: normal end 02h: blank check error 80h: area number specification error [register/memory status after called] entry ram address, area number [call example] when the entry ram address = 0fc30h mov a, #01h ; specifies area 2000h to efffh mov !0fc36h, a mov c, #10h ; flashareablankcheck (function number setting) call !8100h caution area 0 (0000h to 1fffh) is a boot area. do not specify area 0 as an argument. [flowchart] chapter 18 pd78f0988a user? manual u13029ej7v1ud 336 (5) _flashareaprewrite subroutine [function] performs prewrite for a specified area (writes 00h to a specified area). [argument] area number (= 0, 1, 2): 1 byte (offset value: +6) 0: prewrites area 0000h to 1fffh (boot area) 1: prewrites area 2000h to efffh [return value] status (b register) 00h: normal end 08h: write error 80h: area number specification error [register/memory status after called] entry ram address, area number [call example] when the entry ram address = 0fc30h mov a, #1h ; specifies 2000h to efffh mov !0fc36h, a ; mov c, #20h ; flashareaprewrite (function number setting) call !8100h caution area 0 (0000h to 1fffh) is a boot area. do not specify area 0 as an argument. [flowchart] _flashareaprewrite function number = 20h error error no error no error area number check write 00h in specified area verify normal end write error area number specification error chapter 18 pd78f0988a 337 user? manual u13029ej7v1ud (6) _flashareaerase subroutine [function] erases a specified area. [argument] area number (= 0, 1): 1 byte (offset value: +6) 0: erases area 0000h to 1fffh (boot area) 1: erases area 2000h to efffh [return value] status (b register) 00h: normal end 02h: blank check error 04h: overerase check error 80h: area number specification error [register/memory status after called] entry ram address, area number [call example] when the entry ram address = 0fc30h mov a, #1h ; specifies 2000h to efffh mov !0fc36h, a ; mov c, #30h ; flashareaerase (function number setting) call !8100h caution area 0 (0000h to 1fffh) is a boot area. do not specify area 0 as an argument. [flowchart] _flashareaerase function number = 30h error error no error no error area number check erase blank check overerase check normal end blank check error overerase check error area number specification error chapter 18 pd78f0988a user? manual u13029ej7v1ud 338 (7) _flashareawriteback subroutine [function] writes back the flash signature codes. (writeback is an operation to return a flash area in an overerasure status after erasure to the proper erasure status.) [argument] area number (= 0, 1): 1 byte (offset value: +6) [return value] status (b register) 00h: normal end 02h: blank check error 04h: overerase check error 80h: write address error [register/memory status after called] entry ram starting address and area number [call example] when the entry ram address = 0fc30h mov a, #1h ; area 1 setting mov !0fc36h, a ; mov c, #40h ; flashareawriteback (function number setting) call !8100h [notes] set the writeback time to 50 ms/writeback. set the number of writebacks to 30 max., assuming 50 ms/writeback. chapter 18 pd78f0988a 339 user? manual u13029ej7v1ud (8) _flashbytewrite subroutine [function] writes continuously in byte units. [argument] flash memory write start address: 2 bytes (offset value: +2) number of bytes note written in flash memory: 1 byte (offset value: +6) write data storage buffer starting address: 2 bytes (offset value: +14) note if 0 is set, it is possible to set a maximum of 256 bytes. [return value] status (b register) 00h: normal end 08h: write error 80h: write address error [register/memory status after called] entry ram address, number of bytes written in flash memory the flash memory write start address is updated to the address at the end of writing. [call example] when the entry ram address = 0fc30h movw ax, #0fd00h ; write data storage buffer starting address movw !0fc3eh, ax movw ax, #2000h ; flash memory write start address movw !0fc32h, ax mov a, #0h ; number of bytes written in flash memory (256 bytes) mov !0fc36h, a ; mov c, #50h ; flashbytewrite (function number setting) call !8100h chapter 18 pd78f0988a user? manual u13029ej7v1ud 340 _flashbytewrite function number = 50h error error no error no error specified address check write verify normal end write error write address error [flowchart] chapter 18 pd78f0988a 341 user? manual u13029ej7v1ud (9) _flashareaiverify subroutine [function] performs internal verification of a specified area (reads the flash memory of a specified area in a different mode, and compares it). [argument] area number (= 0, 1): 1 byte (offset value: +6) 0: performs internal verification of area 0000h to 1fffh (boot area) 1: performs internal verification of area 2000h to efffh [return value] status (b register) 00h: normal end 10h: verify error 80h: area number specification error [register/memory status after called] entry ram address, area number [call example] when the entry ram address = 0fc30h mov a, #01h ; specifies 2000h to efffh mov !0fc36h, a ; mov c, #60h ; flashareaiverify (function number setting) call !8100h caution area 0 (0000h to 1fffh) is a boot area. do not specify area 0 as an argument. chapter 18 pd78f0988a user? manual u13029ej7v1ud 342 _flashareaiverify function number = 60h error error no error no error area number check read data read data verify normal end verify error area number specification error 18.4.7 self-write circuit configuration the configuration of the self-write circuit is shown in figure 18-18. figure 18-18. self-write circuit configuration [flowchart] pd78f0988a v dd = 5 v 10% v out = 9.7 to 10.2 v v in = 11 to 13.5 v power-supply ic ( pd29s10, etc.) v dd v ss v pp output port 10 k ? 10 k ? output input v ss on/off 343 user? manual u13029ej7v1ud chapter 19 instruction set this chapter lists the instruction set of the pd780988 subseries. for the details of the operation and machine language (instruction code) of each instruction, refer to 78k/0 series user? manual instructions (u12326e) . 19.1 conventions 19.1.1 operand representation and description formats in the operand field of each instruction, an operand is described according to the description format for operand representation of that instruction (for details, refer to the assembler specifications). some operands may be described in two or more description formats. in this case, select one of them. uppercase characters, #, !, $, and [ ] are keywords and must be described as is. the meanings of the symbols are as follows: ? : immediate data $: relative address ? : absolute address [ ]: indirect address when describing immediate data, also describe an appropriate numeric value or label. when describing a label, be sure to describe #, !, $, or [ ]. register description formats r or rp for an operand can be described as a function name (such as x, a, or c) or absolute name (the name in parentheses in the table below, such as r0, r1, or r2). table 19-1. operand representation and description formats representation description format rx (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special function register symbol note sfrp special function register symbol (only even address of register that can be manipulated in 16-bit units) note saddr fe20h to ff1fh immediate data or label saddrp fe20h to ff1fh immediate data or label (even address only) addr16 0000h to ffffh immediate data or label (even address only for 16-bit data transfer instruction) addr11 0800h to 0fffh immediate data or label addr5 0040h to 007fh immediate data or label (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note ffd0h to ffdfh cannot be addressed. remark for the symbols of the special function registers, refer to table 3-4 special function register list . chapter 19 instruction set user? manual u13029ej7v1ud 344 19.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by contents of address or register in ( ) h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 19.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to result r: value saved before is restored chapter 19 instruction set 345 user? manual u13029ej7v1ud mnemonic operand byte operation instruction group 8-bit data transfer 19.2 operation list clock flag note 1 note 2 zaccy mov r, #byte 2 4 r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 7 sfr byte a, r note 3 12 a r r, a note 3 12 r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 5 a sfr sfr, a 2 5 sfr a a, !addr16 3 8 9 + n a (addr16) !addr16, a 3 8 9 + m (addr16) a psw, #byte 3 7 psw byte a, psw 2 5 a psw psw, a 2 5 psw a a, [de] 1 4 5 + n a (de) [de], a 1 4 5 + m (de) a a, [hl] 1 4 5 + n a (hl) [hl], a 1 4 5 + m (hl) a a, [hl + byte] 2 8 9 + n a (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) a a, [hl + b] 1 6 7 + n a (hl + b) [hl + b], a 1 6 7 + m (hl + b) a a, [hl + c] 1 6 7 + n a (hl + c) [hl + c], a 1 6 7 + m (hl + c) a notes 1. when the internal high-speed ram area is accessed or when an instruction that does not access data is executed 2. when an area other than the internal high-speed ram area is accessed 3. except r = a remarks 1. one clock of an instruction is equal to one cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks shown is when the program is stored in the internal rom area. 3. n indicates the number of wait states when the external memory expansion area is read. 4. m indicates the number of wait states when the external memory expansion area is written. chapter 19 instruction set user? manual u13029ej7v1ud 346 mnemonic operand byte operation 8-bit data transfer instruction group 16-bit data transfer 8-bit operation clock flag note 1 note 2 zaccy xch a, r note 3 12 a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 6 a ? sfr a, !addr16 3 8 10 + n + m a ? (addr16) a, [de] 1 4 6 + n + m a ? (de) a, [hl] 1 4 6 + n + m a ? (hl) a, [hl + byte] 2 8 10 + n + m a ? (hl + byte) a, [hl + b] 2 8 10 + n + m a ? (hl + b) a, [hl + c] 2 8 10 + n + m a ? (hl + c) movw rp, #word 3 6 rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 8 ax sfrp sfrp, ax 2 8 sfrp ax ax, rp note 4 14 ax rp rp, ax note 4 14 rp ax ax, !addr16 3 10 12 + 2n ax (addr16) !addr16, ax 3 10 12 + 2m (addr16) ax xchw ax, rp note 4 14 ax ? rp add a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 3 24 a, cy a + r r, a 2 4 r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 + n a, cy a + (saddr16) a, [hl] 1 4 5 + n a, cy a + (hl) a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) a, [hl + b] 2 8 9 + n a, cy a + (hl + b) a, [hl + c] 2 8 9 + n a, cy a + (hl + c) notes 1. when the internal high-speed ram area is accessed or when an instruction that does not access data is executed 2. when an area other than the internal high-speed ram area is accessed 3. except r = a 4. only when rp = bc, de, hl remarks 1. one clock of an instruction is equal to one cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks shown is when the program is stored in the internal rom area. 3. n indicates the number of wait states when the external memory expansion area is read. 4. m indicates the number of wait states when the external memory expansion area is written. chapter 19 instruction set 347 user? manual u13029ej7v1ud mnemonic operand byte operation 8-bit operation instruction group clock flag note 1 note 2 zaccy addc a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 3 24 a, cy a + r + cy r, a 2 4 r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 + n a, cy a + (addr16) + cy a, [hl] 1 4 5 + n a, cy a + (hl) + cy a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 + n a, cy a + (hl + b) + cy a, [hl + c] 2 8 9 + n a, cy a + (hl + c) + cy sub a, #byte 2 4 a, cy a ?byte saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte a, r note 3 24 a, cy a ?r r, a 2 4 r, cy r ?a a, saddr 2 4 5 a, cy a ?(saddr) a, !addr16 3 8 9 + n a, cy a ?(addr16) a, [hl] 1 4 5 + n a, cy a ?(hl) a, [hl + byte] 2 8 9 + n a, cy a ?(hl + byte) a, [hl + b] 2 8 9 + n a, cy a ?(hl + b) a, [hl + c] 2 8 9 + n a, cy a ?(hl + c) subc a, #byte 2 4 a, cy a ?byte ?cy saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte ?cy a, r note 3 24 a, cy a ?r ?cy r, a 2 4 r, cy r ?a ?cy a, saddr 2 4 5 a, cy a ?(saddr) ?cy a, !addr16 3 8 9 + n a, cy a ?(addr16) ?cy a, [hl] 1 4 5 + n a, cy a ?(hl) ?cy a, [hl + byte] 2 8 9 + n a, cy a ?(hl + byte) ?cy a, [hl + b] 2 8 9 + n a, cy a ?(hl + b) ?cy a, [hl + c] 2 8 9 + n a, cy a ?(hl + c) ?cy notes 1. when the internal high-speed ram area is accessed or when an instruction that does not access data is executed 2. when an area other than the internal high-speed ram area is accessed 3. except r = a remarks 1. one clock of an instruction is equal to one cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks shown is when the program is stored in the internal rom area. 3. n indicates the number of wait states when the external memory expansion area is read. chapter 19 instruction set user? manual u13029ej7v1ud 348 mnemonic operand byte operation 8-bit operation instruction group clock flag note 1 note 2 zaccy and a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) or a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) xor a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) notes 1. when the internal high-speed ram area is accessed or when an instruction that does not access data is executed 2. when an area other than the internal high-speed ram area is accessed 3. except r = a remarks 1. one clock of an instruction is equal to one cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks shown is when the program is stored in the internal rom area. 3. n indicates the number of wait states when the external memory expansion area is read. chapter 19 instruction set 349 user? manual u13029ej7v1ud mnemonic operand byte operation 8-bit operation instruction group 16-bit operation multiply/ divide increment/ decrement rotate clock flag note 1 note 2 zaccy cmp a, #byte 2 4 a ?byte saddr, #byte 3 6 8 (saddr) ?byte a, r note 3 24 a r r, a 2 4 r ?a a, saddr 2 4 5 a ?(saddr) a, !addr16 3 8 9 + n a ?(addr16) a, [hl] 1 4 5 + n a ?(hl) a, [hl + byte] 2 8 9 + n a ?(hl + byte) a, [hl + b] 2 8 9 + n a ?(hl + b) a, [hl + c] 2 8 9 + n a ?(hl + c) addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ?word cmpw ax, #word 3 6 ax ?word mulu x216 ax a x divuw c2 25 ax (quotient), c (remainder) ax c inc r12 r r + 1 saddr 2 4 6 (saddr) (saddr) + 1 dec r12 r r ?1 saddr 2 4 6 (saddr) (saddr) ?1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ?1 ror a, 1 1 2 (cy, a 7 a 0 , a m ?1 a m ) 1 time rol a, 1 1 2 (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ?1 a m ) 1 time rolc a, 1 1 2 (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 + n + m a 3-0 (hl) 3-0 , (hl) 7-4 a 3-0 , (hl) 3-0 (hl) 7-4 rol4 [hl] 2 10 12 + n + m a 3-0 (hl) 7-4 , (hl) 3-0 a 3-0 , (hl) 7-4 (hl) 3-0 notes 1. when the internal high-speed ram area is accessed or when an instruction that does not access data is executed 2. when an area other than the internal high-speed ram area is accessed 3. except r = a remarks 1. one clock of an instruction is equal to one cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks shown is when the program is stored in the internal rom area. 3. n indicates the number of wait states when the external memory expansion area is read. 4. m indicates the number of wait states when the external memory expansion area is written. chapter 19 instruction set user? manual u13029ej7v1ud 350 mnemonic operand byte operation bcd adjustment instruction group bit manipulation clock flag note 1 note 2 zaccy adjba 24 decimal adjust accumulator after addition adjbs 24 decimal adjust accumulator after subtract mov1 cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 7 cy sfr.bit cy, a.bit 2 4 cy a.bit cy, psw.bit 3 7 cy psw.bit cy, [hl].bit 2 6 7 + n cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 8 sfr.bit cy a.bit, cy 2 4 a.bit cy psw.bit, cy 3 8 psw.bit cy [hl].bit, cy 2 6 8 + n + m (hl).bit cy and1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit or1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit xor1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit notes 1. when the internal high-speed ram area is accessed or when an instruction that does not access data is executed 2. when an area other than the internal high-speed ram area is accessed remarks 1. one clock of an instruction is equal to one cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks shown is when the program is stored in the internal rom area. 3. n indicates the number of wait states when the external memory expansion area is read. 4. m indicates the number of wait states when the external memory expansion area is written. chapter 19 instruction set 351 user? manual u13029ej7v1ud mnemonic operand byte operation bit manipulation instruction group call/return clock flag note 1 note 2 zaccy set1 saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 8 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 2 6 psw.bit 1 [hl].bit 2 6 8 + n + m (hl).bit 1 clr1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 8 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 2 6 psw.bit 0 [hl].bit 2 6 8 + n + m (hl).bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy call !addr16 3 7 (sp ?1) ( pc + 3) h , (sp ?2) ( pc + 3) l , pc addr16, sp sp ?2 callf !addr11 2 5 (sp ?1) ( pc + 2) h , (sp ?2) ( pc + 2) l , pc 15-11 00001, pc 10-0 addr11, sp sp ?2 callt [addr5] 1 6 (sp ?1) ( pc + 1) h , (sp ?2) ( pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ?2 brk 16 (sp ?1) psw, (sp ?2) (pc + 1) h , (sp ?3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ?3, ie 0 ret 16 pc h (sp + 1), pc l (sp), sp sp + 2 reti 16 pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3, nmis 0 retb 16 pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3 notes 1. when the internal high-speed ram area is accessed or when an instruction that does not access data is executed 2. when an area other than the internal high-speed ram area is accessed remarks 1. one clock of an instruction is equal to one cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks shown is when the program is stored in the internal rom area. 3. n indicates the number of wait states when the external memory expansion area is read. 4. m indicates the number of wait states when the external memory expansion area is written. chapter 19 instruction set user? manual u13029ej7v1ud 352 mnemonic operand byte operation stack manipulation instruction group unconditional branch conditional branch clock flag note 1 note 2 zaccy push psw 1 2 (sp ?1) psw, sp sp ?1 rp 1 4 (sp ?1) rp h , (sp ?2) rp l , sp sp ?2 pop psw 1 2 psw (sp), sp sp + 1 r r r rp 1 4 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, #word 4 10 sp word sp, ax 2 8 sp ax ax, sp 2 8 ax sp br !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 ax 2 8 pc h a, pc l x bc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc pc + 2 + jdisp8 if z = 0 bt saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 9 pc pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 11 pc pc + 4 + jdisp8 if psw.bit = 0 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 0 notes 1. when the internal high-speed ram area is accessed or when an instruction that does not access data is executed 2. when an area other than the internal high-speed ram area is accessed remarks 1. one clock of an instruction is equal to one cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks shown is when the program is stored in the internal rom area. 3. n indicates the number of wait states when the external memory expansion area is read. chapter 19 instruction set 353 user? manual u13029ej7v1ud mnemonic operand byte operation conditional branch instruction group cpu control clock flag note 1 note 2 zaccy btclr saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr16 3 10 12 + n + m pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b, $addr16 2 6 b b ?1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ?1, then pc pc + 2 + jdisp8 if c 0 saddr, $addr16 3 8 10 (saddr) (saddr) ?1, then pc pc + 3 + jdisp8 if (saddr) 0 sel rbn 2 4 rbs1, 0 n nop 12 no operation ei 2 6 ie 1 (enable interrupt) di 2 6 ie 0 (disable interrupt) halt 26 set halt mode stop 26 set stop mode notes 1. when the internal high-speed ram area is accessed or when an instruction that does not access data is executed 2. when an area other than the internal high-speed ram area is accessed remarks 1. one clock of an instruction is equal to one cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the number of clocks shown is when the program is stored in the internal rom area. 3. n indicates the number of wait states when the external memory expansion area is read. 4. m indicates the number of wait states when the external memory expansion area is written. 19.3 instruction list by addressing (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz chapter 19 instruction set user? manual u13029ej7v1ud 354 2nd operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none 1st operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except for r = a chapter 19 instruction set 355 user? manual u13029ej7v1ud (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand 1st operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 #word ax rp note sfrp saddrp !addr16 sp none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none chapter 19 instruction set user? manual u13029ej7v1ud 356 ax !addr16 !addr11 [addr5] $addr16 (4) call/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand 1st operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 357 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v v pp pd78f0988a, 78f0988a(a) only note 1 ?.3 to +10.5 v av dd ?.3 to v dd + 0.3 v av ref ?.3 to v dd + 0.3 v av ss ?.3 to +0.3 v input voltage v i p00 to p03, p10 to p17, p20 to p26, p30 to p37, p50 ?.3 to v dd + 0.3 v to p57, p64 to p67, to70 to to75, x1, x2, reset output voltage v o ?.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss ?0.3 to av ref + 0.3 v and ?.3 to v dd + 0.3 output current, high i oh per pin ?0 ma p00, p01, p30 to p37, p40 to p47, p50 to p57, ?5 ma p64 to p67 total p02, p03, p20 to p26, to70 to to75 total ?5 ma output current, low i ol note 2 p00 to p03, p10 to p17, p20 to p26, peak value 20 ma p30 to p37, p40 to p47, p64 to p67 per pin rms value 10 ma p50 to p57, to70 to to75 per pin peak value 30 ma rms value 15 ma p00, p01, p30 to p37, p40 to p47, peak value 50 ma p64 to p67 total rms value 20 ma p02, p03, p20 to p26 total peak value 30 ma rms value 15 ma to70 to to75 total peak value 100 ma rms value 70 ma p50 to p57 total peak value 100 ma rms value 70 ma operating ambient t a in normal operating mode ?0 to +85 c temperature in flash memory programming mode +10 to +40 c ( pd78f0988a, 78f0988a(a) only) storage temperature t stg mask rom products ?5 to +150 c flash memory products ?0 to +125 c (the notes are explained on the following page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 358 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) notes 1. when writing in the flash memory, be sure to satisfy the following conditions on the v pp voltage supply timing. ? at rising edge of power supply voltage more than 10 s after v dd reaches the lower limit voltage (3.0 v) of the operating voltage range, v pp should exceed v dd (a in the figure below). ? at falling edge of power supply voltage more than 10 s after v pp falls below the lower limit voltage (3.0 v) of the v dd operating voltage range, start up v dd (b in the figure below). 2. the rms value should be calculated as follows: [rms value] = [peak value] duty capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz unmeasured pins returned to 0 v 15 pf i/o capacitance c io f = 1 mhz p00 to p03, p20 to p26, p30 15 pf unmeasured pins to p37, p40 to p47, p50 to returned to 0 v p57, p64 to p67, to70 to to75 remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 3.0 v v dd 0 v 0 v v pp 3.0 v a b 359 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 3.0 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 4.5 v v dd 5.5 v 1.0 12.0 mhz resonator frequency (f x ) note 2 3.0 v v dd < 4.5 v 1.0 8.38 mhz oscillation after v dd reaches 4 ms stabilization oscillation time note 3 voltage range min. crystal oscillation 4.5 v v dd 5.5 v 1.0 12.0 mhz resonator frequency (f x ) note 2 3.0 v v dd < 4.5 v 1.0 8.38 mhz oscillation 4.0 v v dd 5.5 v 10 ms stabilization 3.0 v v dd < 4.0 v 30 ms time note 3 external clock x1 input frequency 4.5 v v dd 5.5 v 1.0 12.0 mhz (f x ) note 2 3.0 v v dd < 4.5 v 1.0 8.38 mhz x1 input high-/low- 4.5 v v dd 5.5 v 38 500 ns level width (t xh , t xl ) 3.0 v v dd < 4.5 v 50 500 ns notes 1. in the case of the pd78f0988a and 78f0988a(a) 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 3. time required to stabilize oscillation after reset or stop mode release. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. x2 x1 c2 x1 x2 test (v pp ) note 1 c1 c2 x1 x2 c1 test (v pp ) note 1 360 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) recommended oscillator constant (1) pd780982, 780983, 780984, 780986, 780988, 780982(a), 780983(a), 780984(a), 780986(a), 780988(a) system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency type recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. cstcc2m00g56-r0 2.00 smd on-chip on-chip 3.0 5.5 co., ltd. cstls2m00g56-b0 2.00 lead on-chip on-chip 3.0 5.5 cstcr4m00g53-r0 4.00 smd on-chip on-chip 3.0 5.5 cstls4m00g53-b0 4.00 lead on-chip on-chip 3.0 5.5 cstcr4m19g53-r0 4.19 smd on-chip on-chip 3.0 5.5 cstls4m19g53-b0 4.19 lead on-chip on-chip 3.0 5.5 cstcr4m91g53-r0 4.91 smd on-chip on-chip 3.0 5.5 cstls4m91g53-b0 4.91 lead on-chip on-chip 3.0 5.5 cstcr5m00g53-r0 5.00 smd on-chip on-chip 3.0 5.5 cstls5m00g53-b0 5.00 lead on-chip on-chip 3.0 5.5 cstce8m00g52-r0 8.00 smd on-chip on-chip 3.0 5.5 cstls8m00g53-b0 8.00 lead on-chip on-chip 3.0 5.5 cstce8m38g52-r0 8.38 smd on-chip on-chip 3.0 5.5 cstls8m38g53-b0 8.38 lead on-chip on-chip 3.0 5.5 cstce10m0g52-r0 10.00 smd on-chip on-chip 4.5 5.5 cstls10m0g53-b0 10.00 lead on-chip on-chip 4.5 5.5 cstce12m0g52-r0 12.00 smd on-chip on-chip 4.5 5.5 cstla12m0t55-b0 12.00 lead on-chip on-chip 4.5 5.5 cstla12m0t55093-b0 12.00 lead on-chip on-chip 4.5 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780988 subseries within the specifications of the dc and ac characteristics. 361 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) (2) pd78f0988a, 78f0988a(a) system clock: ceramic resonator (t a = ? 40 to +85 c) manufacturer part number frequency type recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. cstcc2m00g56-r0 2.00 smd on-chip on-chip 3.0 5.5 co., ltd. cstls2m00g56-b0 2.00 lead on-chip on-chip 3.0 5.5 cstcr4m00g53-r0 4.00 smd on-chip on-chip 3.0 5.5 cstls4m00g53-b0 4.00 lead on-chip on-chip 3.0 5.5 cstcr4m19g53-r0 4.19 smd on-chip on-chip 3.0 5.5 cstls4m19g53-b0 4.19 lead on-chip on-chip 3.0 5.5 cstcr4m91g53-r0 4.91 smd on-chip on-chip 3.0 5.5 cstls4m91g53-b0 4.91 lead on-chip on-chip 3.0 5.5 cstcr5m00g53-r0 5.00 smd on-chip on-chip 3.0 5.5 cstls5m00g53-b0 5.00 lead on-chip on-chip 3.0 5.5 cstce8m00g52-r0 8.00 smd on-chip on-chip 3.0 5.5 cstls8m00g53-b0 8.00 lead on-chip on-chip 3.0 5.5 cstls8m00g53093-b0 8.00 lead on-chip on-chip 3.0 5.5 cstce8m38g52-r0 8.38 smd on-chip on-chip 3.0 5.5 cstls8m38g53-b0 8.38 lead on-chip on-chip 3.0 5.5 cstls8m38g53093-b0 8.38 lead on-chip on-chip 3.0 5.5 cstce10m0g52-r0 10.00 smd on-chip on-chip 4.5 5.5 cstls10m0g53-b0 10.00 lead on-chip on-chip 4.5 5.5 cstls10m0g53093-b0 10.00 lead on-chip on-chip 4.5 5.5 cstce12m0g52-r0 12.00 smd on-chip on-chip 4.5 5.5 cstla12m0t55-b0 12.00 lead on-chip on-chip 4.5 5.5 cstla12m0t55093-b0 12.00 lead on-chip on-chip 4.5 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780988 subseries within the specifications of the dc and ac characteristics. 362 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) dc characteristics (t a = ?0 to +85 c, v dd = 3.0 to 5.5 v) (1/3) parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p37, p40 to p47, p50, p53, 0.7v dd v dd v high p64 to p67 v ih2 reset, p00 to p03, p20, p22, p24 to p26, p51, p52, 0.8v dd v dd v p54 to p57 v ih3 x1, x2 v dd ?0.5 v dd v input voltage, low v il1 p10 to p17, p21, p23, p30 to p37, p40 to p47, p50, p53, 0 0.3v dd v p64 to p67 v il2 reset, p00 to p03, p20, p22, p24 to p26, p51, p52, 0 0.2v dd v p54 to p57 v il3 x1, x2 0 0.4 v output voltage, v oh1 4.5 v v dd 5.5 v, i oh = ? ma v dd ?1.0 v dd v high i oh = ?00 a v dd ?0.5 v dd v output voltage, v ol1 p50 to p57, to70 to to75 4.5 v v dd 5.5 v, 0.4 2.0 v low i ol = 15 ma p00 to p03, p20 to p26, 4.5 v v dd 5.5 v, 0.4 v p30 to p37, p40 to p47, i ol = 1.6 ma p64 to p67 v ol2 i ol = 400 a 0.5 v input leakage i lih1 v in = v dd p00 to p03, p10 to p17, 3 a current, high p20 to p26, p30 to p37, p40 to p47, p50 to p57, p64 to p67, to70 to to75, reset i lih2 x1, x2 20 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, ? a current, low p20 to p26, p30 to p37, p40 to p47, p50 to p57, p64 to p67, to70 to to75, reset i lil2 x1, x2 ?0 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v ? a current, low software pull-up r 2 v in = 0 v 15 30 90 k ? resistor p00 to p03, p20 to p26, p30 to p37, p40 to p47, p50 to p57, p64 to p67 remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 363 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) dc characteristics (t a = ?0 to +85 c, v dd = 3.0 to 5.5 v) (2/3) (1) pd780982, 780983, 780984, 780986, 780988, 780982(a), 780983(a), 780984(a), 780986(a), 780988(a) parameter symbol conditions min. typ. max. unit power supply i dd1 12.0 mhz crystal v dd = 5.0 v 10% note 1 when a/d converter 9 18 note 2 ma current oscillation stopped operating mode when a/d converter 10 20 note 2 ma operating 8.38 mhz crystal v dd = 5.0 v 10% note 1 when a/d converter 6.5 13 note 2 ma oscillation stopped operating mode when a/d converter 7.5 15 note 2 ma operating v dd = 3.0 v 10% note 1, 3 when a/d converter 3.5 7 note 2 ma stopped when a/d converter 4.5 9 note 2 ma operating i dd2 12.0 mhz crystal v dd = 5.0 v 10% note 1 when peripheral 2 4 ma oscillation halt function stopped mode when peripheral 10 ma function operating 8.38 mhz crystal v dd = 5.0 v 10% note 1 when peripheral 1 2 ma oscillation function stopped halt mode when peripheral 7 ma function operating v dd = 3.0 v 10% note 1, 3 when peripheral 0.8 1.5 ma function stopped when peripheral 4.5 ma function operating i dd3 stop mode v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% note 3 0.05 10 a notes 1. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 2. refers to the total current flowing to the internal power supply (v dd0 and v dd1 ). the peripheral operation current is included, but the current flowing to the pull-up resistors of ports and the av ref pin is not. 3. specification when v dd = 3.0 to 3.3 v. the typ. value is the value at v dd = 3.0 v. 364 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) dc characteristics (t a = ?0 to +85 c, v dd = 3.0 to 5.5 v) (3/3) (2) pd78f0988a, 78f0988a(a) parameter symbol conditions min. typ. max. unit power supply i dd1 12.0 mhz crystal v dd = 5.0 v 10% note 1 when a/d converter 25 36 note 2 ma current oscillation stopped operating mode when a/d converter 26 38 note 2 ma operating 8.38 mhz crystal v dd = 5.0 v 10% note 1 when a/d converter 15 25 note 2 ma oscillation stopped operating mode when a/d converter 16 27 note 2 ma operating v dd = 3.0 v 10% note 1, 3 when a/d converter 12 17 note 2 ma stopped when a/d converter 13 19 note 2 ma operating i dd2 12.0 mhz crystal v dd = 5.0 v 10% note 1 when peripheral 2 4 ma oscillation halt function stopped mode when peripheral 10 ma function operating 8.38 mhz crystal v dd = 5.0 v 10% note 1 when peripheral 1.3 2.6 ma oscillation function stopped halt mode when peripheral 7.3 ma function operating v dd = 3.0 v 10% note 1, 3 when peripheral 1 2 ma function stopped when peripheral 5 ma function operating i dd3 stop mode v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% note 3 0.05 10 a v pp supply voltage v pp1 in normal operation mode 0 0.2v dd v notes 1. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 2. refers to the total current flowing to the internal power supply (v dd0 and v dd1 ). the peripheral operation current is included, but the current flowing to the pull-up resistors of ports and the av ref pin is not. 3. specification when v dd = 3.0 to 3.3 v. the typ. value is the value at v dd = 3.0 v. 365 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 3.0 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with system clock 4.5 v v dd 5.5 v 0.166 32 s (min. instruction execution time) 3.0 v v dd < 4.5 v 0.238 32 s ti000, ti001, ti010, f ti0 0f x /64 mhz ti011 input frequency ti000, ti001, ti010, t tih0 2/f sam + s ti011 input high-/ t til0 0.1 note low-level width ti50, ti51, ti52 input f ti5 8-/16-bit precision 0 4 mhz frequency ti50, ti51, ti52 input t tih5 8-/16-bit precision 100 ns high-/low-level width t til5 interrupt request t inth intp0 to intp7 1 s input high-/low-level t intl width toff input high-/low- t toffh 2 s level width t toffl reset input low-level t rsl 10 s width note selection of f sam = f x , f x /4, f x /32 is possible with bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00) or with bits 0 and 1 (prm010, prm011) of prescaler mode register 01 (prm01). note that when selecting ti000 (tm00) or ti001 (tm01) valid edge as the count clock, f sam = f x /16. 366 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) t cy vs v dd (system clock operation) 5.0 1.0 2.0 0.238 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 32.0 10.0 guaranteed operation range 0.166 4.5 367 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) (2) read/write operation (t a = ?0 to +85 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy ?54 ns t add2 (3 + 2n)t cy ?60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy ?87 ns t rdd2 (3 + 2n)t cy ?93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy ?33 ns t rdl2 (2.5 + 2n)t cy ?33 ns wait input time from rd t rdwt1 t cy ?43 ns t rdwt2 t cy ?43 ns wait input time from wr t wrwt t cy ?25 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl (1.5 + 2n)t cy ?15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy ?15 ns delay time from rd at external t rdast 0.8t cy ?15 1.2t cy ns fetch to astb address hold output time from wr t wradh 0.8t cy ?15 1.2t cy + 30 ns write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from rd t rdadh 0.8t cy ?15 1.2t cy + 30 ns at external fetch delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l is the load capacitance of the ad0 to ad7, rd, wr, wait, and astb pins.) caution t cy can only be used when the min. value is 0.238 s. 368 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) (3) serial interface (t a = ?0 to +85 c, v dd = 3.0 to 5.5 v) (a) 3-wire serial i/o mode (sck... internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 4.5 v v dd 5.5 v 5.32 s 3.0 v v dd < 4.5 v 7.63 s sck high-/low-level width t kh1 t kcy1 /2 ?50 ns t kl1 si setup time (to sck )t sik1 100 ns si hold time (from sck )t ksi1 4.5 v v dd 5.5 v 300 ns 3.0 v v dd < 4.5 v 400 ns delay time from sck t kso1 c = 100 pf note 4.5 v v dd 5.5 v 200 ns to so output 3.0 v v dd < 4.5 v 300 ns note c is the load capacitance of the sck and so output lines. (b) 3-wire serial i/o mode (sck... external clock input) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 4.5 v v dd 5.5 v 666 ns 3.0 v v dd < 4.5 v 800 ns sck high-/low-level width t kh2 4.5 v v dd 5.5 v 333 ns t kl2 3.0 v v dd < 4.5 v 400 ns si setup time (to sck )t sik2 100 ns si hold time (from sck )t ksi2 4.5 v v dd 5.5 v 300 ns 3.0 v v dd < 4.5 v 400 ns delay time from sck t kso2 c = 100 pf note 4.5 v v dd 5.5 v 200 ns to so output 3.0 v v dd < 4.5 v 300 ns note c is the load capacitance of the sck and so output lines. (c) uart mode (uart00) (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 187500 bps 3.0 v v dd < 4.5 v 131031 bps (d) uart mode (uart00) (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 115200 bps bit rate allowable error 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: set baud rate (e) uart mode (uart01) (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 93750 bps 3.0 v v dd < 4.5 v 65516 bps 369 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) ac timing test points (excluding x1 input) clock timing ti timing toff timing x1 input v ih3 ( min. ) v il3 ( max. ) 1/f x t xl t xh ti000, ti001, ti010, ti011 ti50, ti51, ti52 1/f ti5 t til5 t tih5 1/f ti0 t til0 t tih0 toff7 t toffl t toffh 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd 370 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) read/write operation external fetch (no wait): external fetch (wait insertion): ad0 to ad7 astb rd 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 operation code t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd ad0 to ad7 astb rd 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad operation code t rdast t astrd t rdl1 t rdh 371 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) external data access (no wait): external data access (wait insertion): read data ad0 to ad7 astb rd wr hi-z hi-z 8-bit address write data t add2 t ads t asth t adh t rdad t rdd2 t rdh t astrd t rdl2 t wds t wdh t wrl t astwr t rdwd t wrwd read data hi-z hi-z 8-bit address write data t add2 t ads t asth t adh t rdad t rdd2 t rdh t astrd t rdl2 t wds t wdh t wrl t wtl t wtl t astwr t rdwd t rdwt2 t wrwd t wrwt t wtwr t wtrd ad0 to ad7 astb rd wr wait 372 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) serial transfer timing 3-wire serial i/o mode: m = 1, 2 si so t kcym t klm t khm t sikm t ksim input data t ksom output data sck 373 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) a/d converter characteristics (t a = ?0 to +85 c, v dd = av dd = 3.0 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1, 2 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr conversion time t conv 4.5 v av dd 5.5 v 12 96 s 4.0 v av dd < 4.5 v 14 96 s 3.0 v av dd < 4.0 v 17 96 s zero-scale error note 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr full-scale error note 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr integral linearity error note 1 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb differential linearity error note 1 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ian 0av ref v reference voltage av ref 2.7 av dd v resistance between av ref r ref when a/d converter is not operating 20 40 k ? and av ss notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 2.0 5.5 v supply voltage data retention i dddr v dddr = 2.0 v 0.1 10 a power supply current release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt request note ms note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). 374 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) interrupt request input timing reset input timing intp0 to intp7 t intl t inth reset t rsl v dd stop instruction execution reset stop mode data retention mode v dddr internal reset operation halt mode operation mode t wait t srel v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr halt mode operation mode t srel t wait 375 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) (1) write erase characteristics parameter symbol conditions min. typ. max. unit operating frequency f x 4.5 v v dd 5.5 v 1.0 10 mhz 3.0 v v dd < 4.5 v 1.0 8.38 mhz v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = v pp2 , f x = 8.38 mhz 40 ma v pp supply current i pp when v pp = v pp2 100 ma step erase time t er note 1 0.199 0.2 0.201 s overall erase time per t era when step erase time = 0.2 s note 2 20 s/area area writeback time t wb note 3 49.4 50 50.6 ms number of writebacks c wb when writeback time = 50 ms note 4 60 times/ per writeback command write- back command number of erase/ c erwb 16 times writebacks step write time t wr note 5 48 50 52 s overall write time per t wrw when step write time = 50 s48 520 s/ word (1 word = 1 byte) note 6 word number of rewrites per c erwr 1 erase + 1 write after erase = 1 rewrite note 7 20 times/ area area notes 1. the recommended setting value for the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (writeback time) is not included. 3. the recommended setting value for the writeback time is 50 ms. 4. writeback is executed once by the issuance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. recommended step write time setting value is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, ?rase write?and ?rite only?are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remarks 1. the range of the operating clock during flash memory programming is not the same as the range during normal operation. 2. when using the pg-fp3, fl-pr3 (made by naito densei), pg-fp4, or fl-pr4 (made by naito densei) the time parameters that need to be downloaded from the parameter files for write/erase are automatically set. unless otherwise directed, do not change the set values. flash memory programming characteristics ( pd78f0988a, 78f0988a(a) only) (t a = 10 to 40 c, v dd = av dd = 3.0 to 5.5 v, v ss = av ss = 0 v, v pp = 9.7 to 10.3 v) 376 user? manual u13029ej7v1ud chapter 20 electrical specifications (expanded-specification products) (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t drpsr v pp high voltage 10 s set time from v pp to reset t psrrf v pp high voltage 1.0 s v pp count start time from reset t rfcf v pp high voltage 1.0 s count execution time t count 20 ms v pp counter high-level width t ch 8.0 s v pp counter low-level width t cl 8.0 s v pp counter noise elimination width t nfw 40 ns flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psrrf t drpsr t ch t cl t count 377 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v v pp pd78f0988a, 78f0988a(a) only note 1 ?.3 to +10.5 v av dd ?.3 to v dd + 0.3 v av ref ?.3 to v dd + 0.3 v av ss ?.3 to +0.3 v input voltage v i p00 to p03, p10 to p17, p20 to p26, p30 to p37, p50 ?.3 to v dd + 0.3 v to p57, p64 to p67, to70 to to75, x1, x2, reset output voltage v o ?.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss ?0.3 to av ref + 0.3 v and ?.3 to v dd + 0.3 output current, high i oh per pin ?0 ma p00, p01, p30 to p37, p40 to p47, p50 to p57, ?5 ma p64 to p67 total p02, p03, p20 to p26, to70 to to75 total ?5 ma output current, low i ol note 2 p00 to p03, p10 to p17, p20 to p26, peak value 20 ma p30 to p37, p40 to p47, p64 to p67 per pin rms value 10 ma p50 to p57, to70 to to75 per pin peak value 30 ma rms value 15 ma p00, p01, p30 to p37, p40 to p47, peak value 50 ma p64 to p67 total rms value 20 ma p02, p03, p20 to p26 total peak value 30 ma rms value 15 ma to70 to to75 total peak value 100 ma rms value 70 ma p50 to p57 total peak value 100 ma rms value 70 ma operating ambient t a in normal operating mode ?0 to +85 c temperature in flash memory programming mode +10 to +40 c ( pd78f0988a, 78f0988a(a) only) storage temperature t stg mask rom products ?5 to +150 c flash memory products ?0 to +125 c (the notes are explained on the following page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 378 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) notes 1. when writing in the flash memory, be sure to satisfy the following conditions on the v pp voltage supply timing. ? at rising edge of power supply voltage more than 10 s after v dd reaches the lower limit voltage (4.0 v) of the operating voltage range, v pp should exceed v dd (a in the figure below). ? at falling edge of power supply voltage more than 10 s after v pp falls below the lower limit voltage (4.0 v) of the v dd operating voltage range, start up v dd (b in the figure below). 2. the rms value should be calculated as follows: [rms value] = [peak value] duty capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz unmeasured pins returned to 0 v 15 pf i/o capacitance c io f = 1 mhz p00 to p03, p20 to p26, p30 15 pf unmeasured pins to p37, p40 to p47, p50 to returned to 0 v p57, p64 to p67, to70 to to75 remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 4.0 v v dd 0 v 0 v v pp 4.0 v a b 379 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 4.0 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 1.0 8.38 mhz resonator frequency (f x ) note 2 oscillation after v dd reaches 4 ms stabilization oscillation time note 3 voltage range min. crystal oscillation 1.0 8.38 mhz resonator frequency (f x ) note 2 oscillation after v dd reaches 10 ms stabilization oscillation time note 3 voltage range min. external clock x1 input frequency 1.0 8.38 mhz (f x ) note 2 x1 input high-/low- 50 500 ns level width (t xh , t xl ) notes 1. in the case of the pd78f0988a and 78f0988a(a) 2. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 3. time required to stabilize oscillation after reset or stop mode release. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. x2 x1 c2 x1 x2 test (v pp ) note 1 c1 c2 x1 x2 c1 test (v pp ) note 1 380 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) recommended oscillator constant (1) pd780982, 780983, 780984, 780986, 780988, 780982(a), 780983(a), 780984(a), 780986(a), 780988(a) system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency type recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. cstcc2m00g56-r0 2.00 smd on-chip on-chip 4.0 5.5 co., ltd. cstls2m00g56-b0 2.00 lead on-chip on-chip 4.0 5.5 cstcr4m00g53-r0 4.00 smd on-chip on-chip 4.0 5.5 cstls4m00g53-b0 4.00 lead on-chip on-chip 4.0 5.5 cstcr4m19g53-r0 4.19 smd on-chip on-chip 4.0 5.5 cstls4m19g53-b0 4.19 lead on-chip on-chip 4.0 5.5 cstcr4m91g53-r0 4.91 smd on-chip on-chip 4.0 5.5 cstls4m91g53-b0 4.91 lead on-chip on-chip 4.0 5.5 cstcr5m00g53-r0 5.00 smd on-chip on-chip 4.0 5.5 cstls5m00g53-b0 5.00 lead on-chip on-chip 4.0 5.5 cstce8m00g52-r0 8.00 smd on-chip on-chip 4.0 5.5 cstls8m00g53-b0 8.00 lead on-chip on-chip 4.0 5.5 cstce8m38g52-r0 8.38 smd on-chip on-chip 4.0 5.5 cstls8m38g53-b0 8.38 lead on-chip on-chip 4.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780988 subseries within the specifications of the dc and ac characteristics. 381 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) (2) pd78f0988a, 78f0988a(a) system clock: ceramic resonator (t a = ? 40 to +85 c) manufacturer part number frequency type recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. cstcc2m00g56-r0 2.00 smd on-chip on-chip 4.0 5.5 co., ltd. cstls2m00g56-b0 2.00 lead on-chip on-chip 4.0 5.5 cstcr4m00g53-r0 4.00 smd on-chip on-chip 4.0 5.5 cstls4m00g53-b0 4.00 lead on-chip on-chip 4.0 5.5 cstcr4m19g53-r0 4.19 smd on-chip on-chip 4.0 5.5 cstls4m19g53-b0 4.19 lead on-chip on-chip 4.0 5.5 cstcr4m91g53-r0 4.91 smd on-chip on-chip 4.0 5.5 cstls4m91g53-b0 4.91 lead on-chip on-chip 4.0 5.5 cstcr5m00g53-r0 5.00 smd on-chip on-chip 4.0 5.5 cstls5m00g53-b0 5.00 lead on-chip on-chip 4.0 5.5 cstce8m00g52-r0 8.00 smd on-chip on-chip 4.0 5.5 cstls8m00g53-b0 8.00 lead on-chip on-chip 4.0 5.5 cstls8m00g53093-b0 8.00 lead on-chip on-chip 4.0 5.5 cstce8m38g52-r0 8.38 smd on-chip on-chip 4.0 5.5 cstls8m38g53-b0 8.38 lead on-chip on-chip 4.0 5.5 cstls8m38g53093-b0 8.38 lead on-chip on-chip 4.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780988 subseries within the specifications of the dc and ac characteristics. 382 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) dc characteristics (t a = ?0 to +85 c, v dd = 4.0 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p37, p40 to p47, p50, p53, 0.7v dd v dd v high p64 to p67 v ih2 reset, p00 to p03, p20, p22, p24 to p26, p51, p52, 0.8v dd v dd v p54 to p57 v ih3 x1, x2 v dd ?0.5 v dd v input voltage, low v il1 p10 to p17, p21, p23, p30 to p37, p40 to p47, p50, p53, 0 0.3v dd v p64 to p67 v il2 reset, p00 to p03, p20, p22, p24 to p26, p51, p52, 0 0.2v dd v p54 to p57 v il3 x1, x2 0 0.4 v output voltage, v oh1 4.5 v v dd 5.5 v, i oh = ? ma v dd ?1.0 v dd v high i oh = ?00 a v dd ?0.5 v dd v output voltage, v ol1 p50 to p57, to70 to to75 4.5 v v dd 5.5 v, 0.4 2.0 v low i ol = 15 ma p00 to p03, p20 to p26, 4.5 v v dd 5.5 v, 0.4 v p30 to p37, p40 to p47, i ol = 1.6 ma p64 to p67 v ol2 i ol = 400 a 0.5 v input leakage i lih1 v in = v dd p00 to p03, p10 to p17, 3 a current, high p20 to p26, p30 to p37, p40 to p47, p50 to p57, p64 to p67, to70 to to75, reset i lih2 x1, x2 20 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, ? a current, low p20 to p26, p30 to p37, p40 to p47, p50 to p57, p64 to p67, to70 to to75, reset i lil2 x1, x2 ?0 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v ? a current, low software pull-up r 2 v in = 0 v 15 30 90 k ? resistor p00 to p03, p20 to p26, p30 to p37, p40 to p47, p50 to p57, p64 to p67 remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 383 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) dc characteristics (t a = ?0 to +85 c, v dd = 4.0 to 5.5 v) (2/2) (1) pd780982, 780983, 780984, 780986, 780988, 780982(a), 780983(a), 780984(a), 780986(a), 780988(a) parameter symbol conditions min. typ. max. unit power supply i dd1 8.38 mhz crystal v dd = 5.0 v 10% note 1 when a/d converter 6.5 13 note 2 ma current oscillation stopped operating mode when a/d converter 7.5 15 note 2 ma operating i dd2 8.38 mhz crystal v dd = 5.0 v 10% note 1 when peripheral 1 2 ma oscillation function stopped halt mode when peripheral 7 ma function operating i dd3 stop mode v dd = 5.0 v 10% 0.1 30 a notes 1. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 2. refers to the total current flowing to the internal power supply (v dd0 and v dd1 ). the peripheral operation current is included, but the current flowing to the pull-up resistors of ports and the av ref pin is not. (2) pd78f0988a, 78f0988a(a) parameter symbol conditions min. typ. max. unit power supply i dd1 8.38 mhz crystal v dd = 5.0 v 10% note 1 when a/d converter 15 25 note 2 ma current oscillation stopped operating mode when a/d converter 16 27 note 2 ma operating i dd2 8.38 mhz crystal v dd = 5.0 v 10% note 1 when peripheral 1.3 2.6 ma oscillation function stopped halt mode when peripheral 7.3 ma function operating i dd3 stop mode v dd = 5.0 v 10% 0.1 30 a v pp supply voltage v pp1 in normal operation mode 0 0.2v dd v notes 1. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 2. refers to the total current flowing to the internal power supply (v dd0 and v dd1 ). the peripheral operation current is included, but the current flowing to the pull-up resistors of ports and the av ref pin is not. 384 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with system clock 0.238 32 s (min. instruction execution time) ti000, ti001, ti010, f ti0 0f x /64 mhz ti011 input frequency ti000, ti001, ti010, t tih0 2/f sam + s ti011 input high-/ t til0 0.1 note low-level width ti50, ti51, ti52 input f ti5 8-/16-bit precision 0 4 mhz frequency ti50, ti51, ti52 input t tih5 8-/16-bit precision 100 ns high-/low-level width t til5 interrupt request t inth intp0 to intp7 1 s input high-/low-level t intl width toff input high-/low- t toffh 2 s level width t toffl reset input low-level t rsl 10 s width note selection of f sam = f x , f x /4, f x /32 is possible with bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00) or with bits 0 and 1 (prm010, prm011) of prescaler mode register 01 (prm01). note that when selecting ti000 (tm00) or ti001 (tm01) valid edge as the count clock, f sam = f x /16. 385 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) t cy vs v dd (system clock operation) 5.0 1.0 2.0 0.238 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 32.0 10.0 guaranteed operation range 386 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) (2) read/write operation (t a = ?0 to +85 c, v dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy ?54 ns t add2 (3 + 2n)t cy ?60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy ?87 ns t rdd2 (3 + 2n)t cy ?93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy ?33 ns t rdl2 (2.5 + 2n)t cy ?33 ns wait input time from rd t rdwt1 t cy ?43 ns t rdwt2 t cy ?43 ns wait input time from wr t wrwt t cy ?25 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl (1.5 + 2n)t cy ?15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy ?15 ns delay time from rd at external t rdast 0.8t cy ?15 1.2t cy ns fetch to astb address hold output time from wr t wradh 0.8t cy ?15 1.2t cy + 30 ns write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from rd t rdadh 0.8t cy ?15 1.2t cy + 30 ns at external fetch delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l is the load capacitance of the ad0 to ad7, rd, wr, wait, and astb pins.) caution t cy can only be used when the min. value is 0.238 s. 387 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) (3) serial interface (t a = ?0 to +85 c, v dd = 4.0 to 5.5 v) (a) 3-wire serial i/o mode (sck... internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 954 ns sck high-/low-level width t kh1 t kcy1 /2 ?50 ns t kl1 si setup time (to sck )t sik1 100 ns si hold time (from sck )t ksi1 400 ns delay time from sck t kso1 c = 100 pf note 300 ns to so output note c is the load capacitance of the sck and so output lines. (b) 3-wire serial i/o mode (sck... external clock input) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 800 ns sck high-/low-level width t kh2 400 ns t kl2 si setup time (to sck )t sik2 100 ns si hold time (from sck )t ksi2 400 ns delay time from sck t kso2 c = 100 pf note 300 ns to so output note c is the load capacitance of the sck and so output lines. (c) uart mode (uart00) (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 125000 bps (d) uart mode (uart00) (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 115200 bps bit rate allowable error 0.87 % output pulse width 1.2 0.24/fbr note s input pulse width 4/f x s note fbr: set baud rate (e) uart mode (uart01) (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 38400 bps 388 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) ac timing test points (excluding x1 input) clock timing ti timing toff timing x1 input v ih3 ( min. ) v il3 ( max. ) 1/f x t xl t xh ti000, ti001, ti010, ti011 ti50, ti51, ti52 1/f ti5 t til5 t tih5 1/f ti0 t til0 t tih0 toff7 t toffl t toffh 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd 389 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) read/write operation external fetch (no wait): external fetch (wait insertion): ad0 to ad7 astb rd 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 operation code t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd ad0 to ad7 astb rd 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad operation code t rdast t astrd t rdl1 t rdh 390 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) external data access (no wait): external data access (wait insertion): read data ad0 to ad7 astb rd wr hi-z hi-z 8-bit address write data t add2 t ads t asth t adh t rdad t rdd2 t rdh t astrd t rdl2 t wds t wdh t wrl t astwr t rdwd t wrwd read data hi-z hi-z 8-bit address write data t add2 t ads t asth t adh t rdad t rdd2 t rdh t astrd t rdl2 t wds t wdh t wrl t wtl t wtl t astwr t rdwd t rdwt2 t wrwd t wrwt t wtwr t wtrd ad0 to ad7 astb rd wr wait 391 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) serial transfer timing 3-wire serial i/o mode: m = 1, 2 si so t kcym t klm t khm t sikm t ksim input data t ksom output data sck 392 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) a/d converter characteristics (t a = ?0 to +85 c, v dd = av dd = 4.0 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1, 2 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr conversion time t conv 4.0 v av dd 5.5 v 14 96 s zero-scale error note 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr full-scale error note 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr integral linearity error note 1 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb differential linearity error note 1 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ian 0av ref v reference voltage av ref 2.7 av dd v resistance between av ref r ref when a/d converter is not operating 20 40 k ? and av ss notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 2.0 5.5 v supply voltage data retention i dddr v dddr = 2.0 v 0.1 10 a power supply current release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt request note ms note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). 393 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) interrupt request input timing reset input timing intp0 to intp7 t intl t inth reset t rsl v dd stop instruction execution reset stop mode data retention mode v dddr internal reset operation halt mode operation mode t wait t srel v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr halt mode operation mode t srel t wait 394 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) (1) write erase characteristics parameter symbol conditions min. typ. max. unit operating frequency f x 1.0 8.38 mhz v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = v pp2 , f x = 8.38 mhz 40 ma v pp supply current i pp when v pp = v pp2 100 ma step erase time t er note 1 0.199 0.2 0.201 s overall erase time per t era when step erase time = 0.2 s note 2 20 s/area area writeback time t wb note 3 49.4 50 50.6 ms number of writebacks c wb when writeback time = 50 ms note 4 60 times/ per writeback command write- back command number of erase/ c erwb 16 times writebacks step write time t wr note 5 48 50 52 s overall write time per t wrw when step write time = 50 s48 520 s/ word (1 word = 1 byte) note 6 word number of rewrites per c erwr 1 erase + 1 write after erase = 1 rewrite note 7 20 times/ area area notes 1. the recommended setting value for the step erase time is 0.2 s. 2. the prewrite time before erasure and the erase verify time (writeback time) is not included. 3. the recommended setting value for the writeback time is 50 ms. 4. writeback is executed once by the issuance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. recommended step write time setting value is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, ?rase write?and ?rite only?are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remarks 1. the range of the operating clock during flash memory programming is the same as the range during normal operation. 2. when using the pg-fp3, fl-pr3 (made by naito densei), pg-fp4, or fl-pr4 (made by naito densei) the time parameters that need to be downloaded from the parameter files for write/erase are automatically set. unless otherwise directed, do not change the set values. flash memory programming characteristics ( pd78f0988a, 78f0988a(a) only) (t a = 10 to 40 c, v dd = av dd = 4.0 to 5.5 v, v ss = av ss = 0 v, v pp = 9.7 to 10.3 v) 395 user? manual u13029ej7v1ud chapter 21 electrical specifications (conventional products) (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t drpsr v pp high voltage 10 s set time from v pp to reset t psrrf v pp high voltage 1.0 s v pp count start time from reset t rfcf v pp high voltage 1.0 s count execution time t count 20 ms v pp counter high-level width t ch 8.0 s v pp counter low-level width t cl 8.0 s v pp counter noise elimination width t nfw 40 ns flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psrrf t drpsr t ch t cl t count user? manual u13029ej7v1ud 396 chapter 22 package drawings i j g h f d n m cb m r 64 33 32 1 l notes p64c-70-750a,c-4 item millimeters b c d f g h j k 1.778 (t.p.) 3.2 0.3 0.51 min. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 0.2 n 0 15 0.50 0.10 0.9 min. r + 0.10 ? 0.05 1. each lead centerline is located within 0.17 mm of its true position (t.p.) at maximum material condition. 2. item "k" to center of leads when formed parallel. a 58.0 + 0.68 ? 0.20 i 4.05 + 0.26 ? 0.20 64-pin plastic sdip (19.05mm(750)) a k chapter 22 package drawings 397 user? manual u13029ej7v1ud 48 49 32 64 1 17 16 33 64-pin plastic qfp (14x14) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.6 0.4 14.0 0.2 0.8 (t.p.) 1.0 j 17.6 0.4 k p64gc-80-ab8-5 c 14.0 0.2 i 0.15 1.8 0.2 l 0.8 0.2 f 1.0 n p q 0.10 2.55 0.1 0.1 0.1 r s 5 5 2.85 max. h 0.37 + 0.08 ? 0.07 m 0.17 + 0.08 ? 0.07 s s n j detail of lead end c d a b r k m l p i s q g f m h chapter 22 package drawings user? manual u13029ej7v1ud 398 64-pin plastic lqfp (14x14) note each lead centerline is located within 0.20 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.2 14.0 0.2 0.8 (t.p.) 1.0 j 17.2 0.2 k c 14.0 0.2 i 0.20 1.6 0.2 l 0.8 f 1.0 n p q 0.10 1.4 0.1 0.127 0.075 u 0.886 0.15 r s 3 1.7 max. t 0.25 p64gc-80-8bs h 0.37 + 0.08 ? 0.07 m 0.17 + 0.03 ? 0.06 s n j t detail of lead end c d a b k m i s p r l u q g f m h + 4 ? 3 1 64 49 17 32 16 48 33 s 399 user? manual u13029ej7v1ud chapter 23 recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 23-1. surface mounting type soldering conditions (1/2) (1) pd78f0988agc-ab8: 64-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-3 (at 210 c or higher), count: three times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-3 (at 200 c or higher), count: three times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). (2) pd780982gc-xxx-8bs: 64-pin plastic lqfp (14 14) pd780983gc-xxx-8bs: 64-pin plastic lqfp (14 14) pd780984gc-xxx-8bs: 64-pin plastic lqfp (14 14) pd780986gc-xxx-8bs: 64-pin plastic lqfp (14 14) pd780988gc-xxx-8bs: 64-pin plastic lqfp (14 14) pd780982gc(a)-xxx-8bs: 64-pin plastic lqfp (14 14) pd780983gc(a)-xxx-8bs: 64-pin plastic lqfp (14 14) pd780984gc(a)-xxx-8bs: 64-pin plastic lqfp (14 14) pd780986gc(a)-xxx-8bs: 64-pin plastic lqfp (14 14) pd780988gc(a)-xxx-8bs: 64-pin plastic lqfp (14 14) pd78f0988agc(a)-ab8: 64-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: two times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: two times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). chapter 23 recommended soldering conditions user? manual u13029ej7v1ud 400 table 23-1. surface mounting type soldering conditions (2/2) (3) pd780982gc-xxx-8bs-a: 64-pin plastic lqfp (14 14) pd780983gc-xxx-8bs-a: 64-pin plastic lqfp (14 14) pd780984gc-xxx-8bs-a: 64-pin plastic lqfp (14 14) pd780986gc-xxx-8bs-a: 64-pin plastic lqfp (14 14) pd780988gc-xxx-8bs-a: 64-pin plastic lqfp (14 14) pd78f0988agc-ab8-a: 64-pin plastic sdip (19.05 mm (750)) pd78f0988agc-8bs-a: 64-pin plastic lqfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) wave soldering for details, contact an nec electronics sales representative. partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remark products that have the part numbers suffixed by ?a?are lead-free products. ir60-207-3 chapter 23 recommended soldering conditions 401 user? manual u13029ej7v1ud table 23-2. insertion type soldering conditions (1) pd780982cw-xxx: 64-pin plastic sdip (19.05 mm (750)) pd780983cw-xxx: 64-pin plastic sdip (19.05 mm (750)) pd780984cw-xxx: 64-pin plastic sdip (19.05 mm (750)) pd780986cw-xxx: 64-pin plastic sdip (19.05 mm (750)) pd780988cw-xxx: 64-pin plastic sdip (19.05 mm (750)) pd78f0988acw: 64-pin plastic sdip (19.05 mm (750)) soldering method soldering condition wave soldering solder bath temperature: 260 c max., time: 10 seconds max. (only for pins) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package. (2) pd780982cw-xxx-a: 64-pin plastic sdip (19.05 mm (750)) pd780983cw-xxx-a: 64-pin plastic sdip (19.05 mm (750)) pd780984cw-xxx-a: 64-pin plastic sdip (19.05 mm (750)) pd780986cw-xxx-a: 64-pin plastic sdip (19.05 mm (750)) pd780988cw-xxx-a: 64-pin plastic sdip (19.05 mm (750)) pd78f0988acw-a: 64-pin plastic sdip (19.05 mm (750)) soldering method soldering condition wave soldering for details, contact an nec electronics sales representative. (only for pins) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution only the pins of the thd are heated when performing wave soldering. make sure that flow solder does not come in contact with the packge. remark products that have the part numbers suffixed by ?a?are lead-free products. user? manual u13029ej7v1ud 402 appendix a development tools the following development tools are available for the development of systems which employ the pd780988 subseries. figure a-1 shows the configuration example of the tools. support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatibles can be used for pc98-nx series computers. when using pc98-nx series computers, refer to the description for ibm pc/at compatibles. windows unless otherwise specified, ?indows?means the following oss. windows 3.1 windows 95 windows 98 windows 2000 windows nt tm ver. 4.0 appendix a development tools 403 user? manual u13029ej7v1ud figure a-1. configuration of development tools notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. language processing software ?assembler package ?c compiler package ?device file ?c library source file note 1 debugging software ?integrated debugger ?system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory ?software package ?project manager (windows only) note 2 software package flash memory write environment control software embedded software ?real-time os i/o board performance board power supply unit appendix a development tools user? manual u13029ej7v1ud 404 a.1 software package sp78k0 this package contains various software tools for 78k/0 series development. software package the following tools are included. ra78k0, cc78k0, id78k0-ns, sm78k0, and various device files part number: s sp78k0 remark in the part number differs depending on the os used. s sp78k0 host machine os supply medium ab17 pc-9800 series, windows (japanese version) cd-rom bb17 ibm pc/at compatibles windows (english version) a.2 language processing software ra78k0 assembler package cc78k0 c compiler package df780988 note 1 device file cc78k0-l note 2 c library source file notes 1. the df780988 can be used in common with the ra78k0, cc78k0, sm78k0, id78k0-ns, id78k0, and rx78k0. 2. cc78k0-l is not included in the software package (sp78k0). this assembler converts programs written in mnemonics into object codes executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with an optional device file (df780988). appendix a development tools 405 user? manual u13029ej7v1ud flash programmer dedicated to microcontrollers with on-chip flash memory. ?fa-64gc-8bs-a: 64-pin plastic lqfp (gc-8bs type) remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df780988 s cc78k0-l host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at compatibles windows (english version) 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4), 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt a.3 control software project manager this is control software designed to enable efficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. appendix a development tools user? manual u13029ej7v1ud 406 a.5 debugging tools (hardware) a.5.1 when using the in-circuit emulator ie-78k0-ns or ie-78k0-ns-a ie-78k0-ns in-circuit emulator ie-78k0-ns-pa performance board ie-78k0-ns-a in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if-a pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-780988-ns-em4 emulation board ie-78k0-ns-p01 i/o board np-64cw emulation probe np-64gc-tq np-h64gc-tq emulation tgc-064sap probe conversion adapter (refer to figure a-4 ) remarks 1. np-64cw, np-64gc, np-64gc-tq, and np-h64gc-tq are products of naito densei machida mfg. co., ltd. for further information, contact naito densei machida mfg. co., ltd. (+81-45-475-4191) 2. tgc-064sap is a product made by tokyo eletech corporation. for further information, contact daimaru kogyo co., ltd. tokyo electronics department (+81-3-3820-7112) osaka electronics department (+81-6-6244-6672) 3. the tgc-064sap is sold in single units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it is supported by the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and interface adapter, which is required to connect this emulator to the host machine. this board is used to enhance the functions of the ie-78k0-ns. by connecting this board to the ie-78k0-ns-pa before use, debugging functions, such as coverage function addition and the enhancement of tracer and timer functions, are enhanced. in-circuit emulator that combines ie-78k0-ns and ie-78k0-ns-pa this adapter is used for supplying power from a receptacle of 100 v to 240 v ac. this adapter is required when using a pc-9800 series computer (except notebook type) as the host machine (c bus supported). this pc card and interface cable are required when using a notebook-type computer as the host machine (pcmcia socket supported). this adapter is required when using an ibm pc/at or compatible computer as the host machine (isa bus supported). this adapter is required when using a pci bus integrated computer as the host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator and ie-78k0-ns-p01. this board is used in combination with the ie-780988-ns-em4 and ie-78k0-ns to perform emulation. this probe is used to connect the in-circuit emulator to the target system and is designed for a 64-pin plastic sdip (cw type). this probe is used to connect the in-circuit emulator to the target system and is designed for a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this conversion adapter connects the np-64gc-tq and np-h64gc-tq to the target system board designed to mount a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). appendix a development tools 407 user? manual u13029ej7v1ud a.5.2 when using the in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator ie-70000-98-if-c interface adapter ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-78000-r-sv3 interface adapter ie-780988-ns-em4 emulation board ie-78k0-ns-p01 i/o board ie-78k0-r-ex1 emulation probe conversion board ep-78240cw-r emulation probe ep-78240gc-r emulation probe ev-9200gc-64 conversion socket (refer to figures a-2 and a-3 ) remark the ev-9200gc-64 is sold in packages of 5 units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it is supported by the integrated debugger (id78k0). this emulator should be used in combination with an emulation probe and interface adapter, which is required to connect this emulator to the host machine. this adapter is required when using a pc-9800 series computer (except notebook type) as the ie-78001-r-a host machine (c bus supported). this adapter is required when using an ibm pc/at or compatible computer as the ie- 78001-r-a host machine (isa bus supported). this adapter is required when using a pci bus integrated computer as the ie-78001-r-a host machine. this is the adapter and cable required when using an ews computer as the ie-78001- r-a host machine, and is used connected to the board in the ie-78001-r-a. 10base-5 is supported for ethernet tm . for other methods, a commercially available conversion adapter is required. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator, ie-78k0-ns-p01, and ie-78k0-r-ex1. this board is used in combination with the ie-780988-ns-em4 and ie-78k0-ns to perform emulation. this board is required when using the ie-780988-ns-em4 and ie-78k0-ns-p01 on the ie-78001-r-a. this probe is used to connect the in-circuit emulator to the target system and is designed for a 64-pin plastic sdip (cw type). this probe is used to connect the in-circuit emulator to the target system and is designed for a 64-pin plastic qfp (gc-ab8 type). this conversion socket connects the ep-78240gc-r to the target system board designed to mount a 64-pin plastic qfp (gc-ab8 type). appendix a development tools user? manual u13029ej7v1ud 408 a.6 debugging tools (software) sm78k0 this is a system simulator for the 78k/0 series. the sm78k0 is windows-based system simulator software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with the device file (df780988) (sold separately). part number: s sm78k0 id78k0-ns this debugger supports the in-circuit emulators for the 78k/0 series. the integrated debugger id78k0-ns is windows-based software. (supporting in-circuit emulators it has improved c-compatible debugging functions and can display the results of ie-78k0-ns and ie-78k0-ns-a) tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. it should be used in combination with the device file (df780988) (sold separately). part number: s id78k0-ns, s id78k0 remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns s id78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) id78k0 integrated debugger (supporting in-circuit emulator ie-78001-r-a) appendix a development tools 409 user? manual u13029ej7v1ud a.7 embedded software rx78k0 rx78k0 is a real-time os conforming to the itron specifications. real-time os tool (configurator) for generating nucleus of rx78k0 and plural information tables is supplied. used in combination with an optional assembler package (ra78k0) and device file (df780988). appendix a development tools user? manual u13029ej7v1ud 410 a.8 upgrading from former in-circuit emulator for 78k/0 series to ie-78001-r-a if you already have a former in-circuit emulator for 78k/0 series microcontrollers (ie-78000-r or ie-78000-r-a), that in-circuit emulator can operate as equivalent to the ie-78001-r-a by replacing its internal break board with the ie-78001-r-bk. table a-1. upgrading from former in-circuit emulator for 78k/0 series to ie-78001-r-a in-circuit emulator owned in-circuit emulator cabinet system upgrade note board to be purchased ie-78000-r required ie-78001-r-bk ie-78000-r-a not required note to replace the cabinet, send your in-circuit emulator to nec electronics corporation. appendix a development tools 411 user? manual u13029ej7v1ud a.9 package drawings for conversion socket and conversion adapter figure a-2. ev-9200gc-64 package drawing (for reference only) a f 1 e ev-9200gc-64 b d c m n l k r q i h p o s t j g no.1 pin index ev-9200gc-64-g0 item millimeters inches a b c d e f g h i j k l m n o p q r s t 18.8 14.1 14.1 18.8 4-c 3.0 0.8 6.0 15.8 18.5 6.0 15.8 18.5 8.0 7.8 2.5 2.0 1.35 0.35 0.1 2.3 1.5 0.74 0.555 0.555 0.74 4-c 0.118 0.031 0.236 0.622 0.728 0.236 0.622 0.728 0.315 0.307 0.098 0.079 0.053 0.014 0.091 0.059 +0.004 ?.005 appendix a development tools user? manual u13029ej7v1ud 412 figure a-3. ev-9200gc-64 footprints (for reference only) f e d g h i j k l c b a 0.031 0.591=0.472 0.031 0.591=0.472 ev-9200gc-64-p1e item millimeters inches a b c d e f g h i j k l 19.5 14.8 14.8 19.5 6.00 0.08 6.00 0.08 0.5 0.02 2.36 0.03 2.2 0.1 1.57 0.03 0.768 0.583 0.583 0.768 0.236 0.236 0.197 0.093 0.087 0.062 0.8 0.02 15=12.0 0.05 0.8 0.02 15=12.0 0.05 +0.002 ?.001 +0.003 ?.002 +0.002 ?.001 +0.003 ?.002 +0.004 ?.003 +0.004 ?.003 +0.001 ?.002 +0.001 ?.002 +0.004 ?.005 +0.001 ?.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to ?emiconductor device mounting technology manual?(http://www.necel.com/pkg/en/mount/index.html). caution appendix a development tools 413 user? manual u13029ej7v1ud figure a-4. tgc-064sap package drawing (for reference only) note made by tokyo eletech corporation. item millimeters inches b3.5 0.138 c2.0 0.079 a1.85 0 .073 d6.0 0.236 e0.25 0 .010 f 13.6 g1.2 0.047 0.535 item millimeters inches b 0.8x15=12.0 0.031x0.591=0.472 c0.8 0.031 a 14.12 0.556 d h 17.2 0.677 ic 2.0 c 0.079 j9.05 0 .356 e 10.0 0.394 f 12.4 0.488 k5.0 0.197 l 13.35 0.526 m q 12.5 0.492 r 17.5 0.689 s n1. 325 0.052 o 16.0 p 20.65 0.813 4- 1.3 4- 0.051 0.630 w x( 19.65) (0.667) y7.35 0 .289 t u v z1.2 0.047 20.65 1.325 0.813 0.052 g 14.8 0.583 reference diagram: tgc-064sap (tqpack064sa+tqsocket064sap) package dimension (unit: mm) v c i j i a eg h f b c w z mn ? 1.8 0.071 3.55 0.140 ? 0.9 0.035 ? 0.3 0.012 ? h1.2 0.047 i2.4 j2.7 0.106 0.094 tgc-064sap-g0e protrusion height a b u g h q r f e d l o k t s j p x y d user? manual u13029ej7v1ud 414 appendix b notes on designing target system the connection condition diagrams for an emulation probe, conversion connector, and conversion socket or conversion adapter are shown below. design the system taking into consideration the dimension or shape, etc. of the parts to be mounted on the target system. table b-1. distance between in-circuit emulator and conversion socket or conversion adapter emulation probe conversion adapter, distance between in-circuit emulator conversion socket and conversion socket or conversion adapter np-64gc-tq tgc-064sap 170 mm np-h64gc-tq 370 mm np-64cw 160 mm figure b-1. distance between in-circuit emulator and conversion socket or conversion adapter (1) in-circuit emulator: ie-78k0-ns or ie-78k0-ns-a emulation probe: np-64gc-tq emulation board: ie-780988-ns-em4 cn6 170 mm t arget system (64gc) conversion adapter: tgc-064sap appendix b notes on designing target system 415 user? manual u13029ej7v1ud figure b-2. distance between in-circuit emulator and conversion socket or conversion adapter (2) figure b-3. distance between in-circuit emulator and conversion socket or conversion adapter (3) in-circuit emulator: ie-78k0-ns or ie-78k0-ns-a emulation probe: np-h64gc-tq conversion adapter: tgc-064sap emulation board: ie-780988-ns-em4 cn6 370 mm t arget system (64gc) in-circuit emulator: ie-78k0-ns or ie-78k0-ns-a emulation probe: np-64cw emulation board: ie-780988-ns-em4 cn7 160 mm t arget system (64cw) ic socket appendix b notes on designing target system user? manual u13029ej7v1ud 416 figure b-4. connection condition of target system (1) 34 mm 17 mm 1 pin emulation probe: np-64gc-tq emulation board: ie-780988-ns-em4 25 mm 34 mm 40 mm 23 mm 65 mm t arget system 11 mm 17 mm conversion adapter: tgc-064sap appendix b notes on designing target system 417 user? manual u13029ej7v1ud figure b-5. connection condition of target system (2) figure b-6. connection condition of target system (3) 1 pin emulation board: ie-780988-ns-em4 23 mm 17 mm 17 mm 45 mm 11 mm 42 mm 10.0 mm 45 mm 52 mm conversion adapter: tgc-064sap t arget system emulation probe: np-h64gc-tq emulation probe: np-64cw emulation board: ie-780988-ns-em4 20 mm 33 mm 24 mm 13 mm 8 mm 34 mm 14 mm 40 mm 25 mm 34 mm ta rget system user? manual u13029ej7v1ud 418 appendix c register index c.1 register index (in alphabetical order with respect to register name) [a] a/d conversion result register 0 (adcr0) ................................................................................................. 204 a/d converter mode register 0 (adm0) ..................................................................................................... 205 analog input channel specification register 0 (ads0) .............................................................................. 207 asynchronous serial interface mode register 0 (asim00) ....................................................... 227, 234, 235 asynchronous serial interface mode register 1 (asim01) ....................................................... 227, 234, 235 asynchronous serial interface status register 0 (asis00) .............................................................. 230, 237 asynchronous serial interface status register 1 (asis01) .............................................................. 230, 237 [b] baud rate generator control register 0 (brgc00) ........................................................................... 231, 238 baud rate generator control register 1 (brgc01) ........................................................................... 231, 238 [c] capture/compare control register 00 (crc00) ......................................................................................... 113 capture/compare control register 01 (crc01) ......................................................................................... 113 [d] dc control register 0 (dcctl0) ................................................................................................................. 189 dc control register 1 (dcctl1) ................................................................................................................. 190 dead-time reload register (dtime) ............................................................................................................ 162 [e] 8-bit compare register 50 (cr50) ............................................................................................................... 141 8-bit compare register 51 (cr51) ............................................................................................................... 141 8-bit compare register 52 (cr52) ............................................................................................................... 141 8-bit timer counter 50 (tm50) ..................................................................................................................... 141 8-bit timer counter 51 (tm51) ..................................................................................................................... 141 8-bit timer counter 52 (tm52) ..................................................................................................................... 141 8-bit timer mode control register 50 (tmc50) ........................................................................................... 142 8-bit timer mode control register 51 (tmc51) ........................................................................................... 142 8-bit timer mode control register 52 (tmc52) ........................................................................................... 142 external interrupt falling edge enable register (egn) .............................................................................. 268 external interrupt falling edge enable register 5 (egn5) ......................................................................... 269 external interrupt rising edge enable register (egp) ............................................................................... 268 external interrupt rising edge enable register 5 (egp5) .......................................................................... 269 [f] flash programming mode control register (flpmc) ................................................................................ 324 [i] internal expansion ram size switching register (ixs) ............................................................................. 307 appendix c register index 419 user? manual u13029ej7v1ud interrupt mask flag register 0h (mk0h) ..................................................................................................... 266 interrupt mask flag register 0l (mk0l) ...................................................................................................... 266 interrupt mask flag register 1l (mk1l) ...................................................................................................... 266 interrupt request flag register 0h (if0h) ................................................................................................... 265 interrupt request flag register 0l (if0l) ..................................................................................................... 265 interrupt request flag register 1l (if1l) ..................................................................................................... 265 inverter timer control register 7 (tmc7) .................................................................................................... 163 inverter timer mode register 7 (tmm7) ...................................................................................................... 165 [m] memory expansion mode register (mem) .................................................................................................. 284 memory expansion wait setting register (mm) .......................................................................................... 285 memory size switching register (ims) ............................................................................................... 286, 306 [o] oscillation stabilization time select register (osts) ....................................................................... 177, 294 [p] port 0 (p0) ............................................................................................................................... ....................... 87 port 1 (p1) ............................................................................................................................... ....................... 88 port 2 (p2) ............................................................................................................................... ....................... 89 port 3 (p3) ............................................................................................................................... ....................... 90 port 4 (p4) ............................................................................................................................... ....................... 91 port 5 (p5) ............................................................................................................................... ....................... 92 port 6 (p6) ............................................................................................................................... ....................... 94 port mode register 0 (pm0) ........................................................................................................................... 95 port mode register 2 (pm2) .................................................................................................................. 95, 148 port mode register 3 (pm3) .................................................................................................................. 95, 185 port mode register 4 (pm4) ........................................................................................................................... 95 port mode register 5 (pm5) .................................................................................................................. 95, 119 port mode register 6 (pm6) ........................................................................................................................... 95 prescaler mode register 00 (prm00) ......................................................................................................... 117 prescaler mode register 01 (prm01) ......................................................................................................... 117 priority specification flag register 0h (pr0h) ........................................................................................... 267 priority specification flag register 0l (pr0l) ............................................................................................. 267 priority specification flag register 1l (pr1l) ............................................................................................. 267 processor clock control register (pcc) ........................................................................................................ 99 program status word (psw) ................................................................................................................ 63, 270 pull-up resistor option register 0 (pu0) ....................................................................................................... 96 pull-up resistor option register 2 (pu2) ....................................................................................................... 96 pull-up resistor option register 3 (pu3) ....................................................................................................... 96 pull-up resistor option register 4 (pu4) ....................................................................................................... 96 pull-up resistor option register 5 (pu5) ....................................................................................................... 96 pull-up resistor option register 6 (pu6) ....................................................................................................... 96 [r] real-time output buffer register 0h (rtbh00) .......................................................................................... 183 real-time output buffer register 0l (rtbl00) ........................................................................................... 183 appendix c register index user? manual u13029ej7v1ud 420 real-time output buffer register 1h (rtbh01) .......................................................................................... 184 real-time output buffer register 1l (rtbl01) ........................................................................................... 184 real-time output port control register 0 (rtpc00) ................................................................................... 187 real-time output port control register 1 (rtpc01) ................................................................................... 188 real-time output port mode register 0 (rtpm00) ..................................................................................... 185 real-time output port mode register 1 (rtpm01) ..................................................................................... 186 receive buffer register 0 (rxb00) ............................................................................................................. 226 receive buffer register 1 (rxb01) ............................................................................................................. 226 [s] serial i/o shift register 3 (sio3) ................................................................................................................. 252 serial operation mode register 3 (csim3) ................................................................................ 253, 255, 256 16-bit capture/compare register 000 (cr000) ........................................................................................... 108 16-bit capture/compare register 001 (cr001) ........................................................................................... 108 16-bit capture/compare register 010 (cr010) ........................................................................................... 110 16-bit capture/compare register 011 (cr011) ........................................................................................... 110 16-bit timer counter 00 (tm00) ................................................................................................................... 108 16-bit timer counter 01 (tm01) ................................................................................................................... 108 16-bit timer mode control register 00 (tmc00) ......................................................................................... 110 16-bit timer mode control register 01 (tmc01) ......................................................................................... 110 [t] 10-bit buffer register 0 (bfcm0) ................................................................................................................. 162 10-bit buffer register 1 (bfcm1) ................................................................................................................. 162 10-bit buffer register 2 (bfcm2) ................................................................................................................. 162 10-bit buffer register 3 (bfcm3) ................................................................................................................. 162 10-bit compare register 0 (cm0) ................................................................................................................. 161 10-bit compare register 1 (cm1) ................................................................................................................. 161 10-bit compare register 2 (cm2) ................................................................................................................. 161 10-bit compare register 3 (cm3) ................................................................................................................ 162 timer clock select register 50 (tcl50) ...................................................................................................... 146 timer clock select register 51 (tcl51) ...................................................................................................... 146 timer clock select register 52 (tcl52) ...................................................................................................... 146 timer output control register 00 (toc00) ................................................................................................. 115 timer output control register 01 (toc01) ................................................................................................. 115 transmit shift register 0 (txs00) ............................................................................................................... 226 transmit shift register 1 (txs01) ............................................................................................................... 226 [w] watchdog timer clock select register (wdcs) .......................................................................................... 175 watchdog timer mode register (wdtm) .................................................................................................... 176 appendix c register index 421 user? manual u13029ej7v1ud c.2 register index (in alphabetical order with respect to register symbol) [a] adcr0: a/d conversion result register 0 ................................................................................................ 204 ads0: analog input channel specification register 0 ........................................................................... 207 adm0: a/d converter mode register 0 ................................................................................................... 205 asim00: asynchronous serial interface mode register 0 ....................................................... 227, 234, 235 asim01: asynchronous serial interface mode register 1 ....................................................... 227, 234, 235 asis00: asynchronous serial interface status register 0 .............................................................. 230, 237 asis01: asynchronous serial interface status register 1 .............................................................. 230, 237 [b] bfcm0: 10-bit buffer register 0 ................................................................................................................ 162 bfcm1: 10-bit buffer register 1 ................................................................................................................ 162 bfcm2: 10-bit buffer register 2 ................................................................................................................ 162 bfcm3: 10-bit buffer register 3 ................................................................................................................ 162 brgc00: baud rate generator control register 0 ............................................................................. 231, 238 brgc01: baud rate generator control register 1 ............................................................................. 231, 238 [c] cm0: 10-bit compare register 0 ........................................................................................................... 161 cm1: 10-bit compare register 1 ........................................................................................................... 161 cm2: 10-bit compare register 2 ........................................................................................................... 161 cm3: 10-bit compare register 3 ........................................................................................................... 162 cr000: 16-bit capture/compare register 000 ......................................................................................... 108 cr001: 16-bit capture/compare register 001 ......................................................................................... 108 cr010: 16-bit capture/compare register 010 ......................................................................................... 110 cr011: 16-bit capture/compare register 011 ......................................................................................... 110 cr50: 8-bit compare register 50 ........................................................................................................... 141 cr51: 8-bit compare register 51 ........................................................................................................... 141 cr52: 8-bit compare register 52 ........................................................................................................... 141 crc00: capture/compare control register 00 ......................................................................................... 113 crc01: capture/compare control register 01 ......................................................................................... 113 csim3: serial operation mode register 3 .............................................................................. 253, 255, 256 [d] dcctl0: dc control register 0 ................................................................................................................... 189 dcctl1: dc control register 1 ................................................................................................................... 190 dtime: dead-time reload register ........................................................................................................... 162 [e] egn: external interrupt falling edge enable register ......................................................................... 268 egn5: external interrupt falling edge enable register 5 ...................................................................... 269 egp: external interrupt rising edge enable register .......................................................................... 268 egp5: external interrupt rising edge enable register 5 ....................................................................... 269 [f] flpmc: flash programming mode control register ................................................................................ 324 appendix c register index user? manual u13029ej7v1ud 422 [i] if0h: interrupt request flag register 0h ............................................................................................... 265 if0l: interrupt request flag register 0l ............................................................................................... 265 if1l: interrupt request flag register 1l ............................................................................................... 265 ims: memory size switching register ......................................................................................... 286, 306 ixs: internal expansion ram size switching register ..................................................................... 307 [m] mem: memory expansion mode register .............................................................................................. 284 mk0h: interrupt mask flag register 0h .................................................................................................. 266 mk0l: interrupt mask flag register 0l ................................................................................................... 266 mk1l: interrupt mask flag register 1l ................................................................................................... 266 mm: memory expansion wait setting register .................................................................................... 285 [o] osts: oscillation stabilization time select register ..................................................................... 177, 294 [p] p0: port 0 ............................................................................................................................... ............... 87 p1: port 1 ............................................................................................................................... ............... 88 p2: port 2 ............................................................................................................................... ............... 89 p3: port 3 ............................................................................................................................... ............... 90 p4: port 4 ............................................................................................................................... ............... 91 p5: port 5 ............................................................................................................................... ............... 92 p6: port 6 ............................................................................................................................... ............... 94 pcc: processor clock control register ................................................................................................... 99 pm0: port mode register 0 ..................................................................................................................... 95 pm2: port mode register 2 ............................................................................................................ 95, 148 pm3: port mode register 3 ............................................................................................................ 95, 185 pm4: port mode register 4 ..................................................................................................................... 95 pm5: port mode register 5 ............................................................................................................ 95, 119 pm6: port mode register 6 ..................................................................................................................... 95 pr0h: priority specification flag register 0h ........................................................................................ 267 pr0l: priority specification flag register 0l ......................................................................................... 267 pr1l: priority specification flag register 1l ......................................................................................... 267 prm00: prescaler mode register 00 ........................................................................................................ 117 prm01: prescaler mode register 01 ........................................................................................................ 117 psw: program status word ............................................................................................................ 63, 270 pu0: pull-up resistor option register 0 .................................................................................................. 96 pu2: pull-up resistor option register 2 .................................................................................................. 96 pu3: pull-up resistor option register 3 .................................................................................................. 96 pu4: pull-up resistor option register 4 .................................................................................................. 96 pu5: pull-up resistor option register 5 .................................................................................................. 96 pu6: pull-up resistor option register 6 .................................................................................................. 96 [r] rtbh00: real-time output buffer register 0h ........................................................................................... 183 rtbh01: real-time output buffer register 1h ........................................................................................... 184 appendix c register index 423 user? manual u13029ej7v1ud rtbl00: real-time output buffer register 0l ............................................................................................ 183 rtbl01: real-time output buffer register 1l ............................................................................................ 184 rtpc00: real-time output port control register 0 .................................................................................... 187 rtpc01: real-time output port control register 1 .................................................................................... 188 rtpm00: real-time output port mode register 0 ...................................................................................... 185 rtpm01: real-time output port mode register 1 ...................................................................................... 186 rxb00: receive buffer register 0 ............................................................................................................ 226 rxb01: receive buffer register 1 ............................................................................................................ 226 [s] sio3: serial i/o shift register 3 ............................................................................................................. 252 [t] tcl50: timer clock select register 50 .................................................................................................... 146 tcl51: timer clock select register 51 .................................................................................................... 146 tcl52: timer clock select register 52 .................................................................................................... 146 tm00: 16-bit timer counter 00 ................................................................................................................ 108 tm01: 16-bit timer counter 01 ................................................................................................................ 108 tm50: 8-bit timer counter 50 .................................................................................................................. 141 tm51: 8-bit timer counter 51 .................................................................................................................. 141 tm52: 8-bit timer counter 52 .................................................................................................................. 141 tmc00: 16-bit timer mode control register 00 ........................................................................................ 110 tmc01: 16-bit timer mode control register 01 ........................................................................................ 110 tmc50: 8-bit timer mode control register 50 .......................................................................................... 142 tmc51: 8-bit timer mode control register 51 .......................................................................................... 142 tmc52: 8-bit timer mode control register 52 .......................................................................................... 142 tmc7: inverter timer control register 7 .................................................................................................. 163 tmm7: inverter timer mode register 7 .................................................................................................... 165 toc00: timer output control register 00 ................................................................................................. 115 toc01: timer output control register 01 ................................................................................................. 115 txs00: transmit shift register 0 .............................................................................................................. 226 txs01: transmit shift register 1 .............................................................................................................. 226 [w] wdcs: watchdog timer clock select register ........................................................................................ 175 wdtm: watchdog timer mode register ................................................................................................... 176 user? manual u13029ej7v1ud 424 appendix d revision history a history of the revisions up to this edition is shown below. ?pplied to:?indicates the chapters to which the revision was applied. (1/6) edition contents applied to: 3rd change of status from ?nder development?to ?evelopment completed?for the throughout following products pd780982, 780983, and 780984 1.4 pin configuration (top view) chapter 1 deletion of cautions for av dd and av ss connections general 2.1 list of pin functions (2) non-port pins chapter 2 modification of descriptions for ti000, ti001, av dd , av ss pins pin functions 2.2.5 p40 to p47 (port 4) modification of description for (2) control mode addition of i/o circuit type description to table 2-1 types of pin i/o circuits addition of figure 2-1 pin i/o circuit modification of description for tmc50, tmc51, tmc52 in table 3-4 special chapter 3 function register list cpu architecture 4.3 registers controlling port functions chapter 4 addition of caution to (1) port mode registers (pm0, pm2, pm3, pm4, pm5, pm6) port functions addition of caution to (2) pull-up resistor option registers (pu0, pu2, pu3, pu4, pu5, pu6) modification of figure 4-11 format of pull-up resistor option register 6.3 configuration of 16-bit timer/event counter chapter 6 modification of table 6-3 ti00n pin valid edge and cr00n, cr01n capture 16-bit timer/event triggers counter modification of caution in (3) 16-bit capture/compare register 010, 011 (cr010, cr011) addition of caution to figure 6-5 format of capture/compare control register 00 addition of caution to figure 6-6 format of capture/compare control register 01 addition of cautions to figure 6-7 format of timer output control register 00 addition of cautions to figure 6-8 format of timer output control register 01 addition of note to figure 6-9 format of prescaler mode register 00 addition of note to figure 6-10 format of prescaler mode register 01 modification of figure 6-13 interval timer configuration diagram modification of description in 6.5.4 external event counter operation modification of figure 6-27 external event counter configuration diagram 6.6 notes on 16-bit timer/event counter addition of description to (6) one-shot pulse output addition of description to (10) capture operation addition of description to (12) edge detection 7.2 configuration of 8-bit timer/event counter chapter 7 modification of (2) 8-bit compare registers 50, 51, and 52 (cr50, cr51, and cr52) 8-bit timer/event 7.3 registers controlling 8-bit timer/event counter counter modification of (1) 8-bit timer mode control registers 50, 51, and 52 (tmc50, tmc51, and tmc52) modification of figure 7-4 format of 8-bit timer mode control register 50 modification of figure 7-5 format of 8-bit timer mode control register 51 modification of figure 7-6 format of 8-bit timer mode control register 52 appendix d revision history 425 user? manual u13029ej7v1ud (2/6) edition contents applied to: 3rd 8.4 operation of 10-bit inverter control timer chapter 8 modification of caution in (2) output waveform widths corresponding to set 10-bit inverter values control timer modification of figure 8-6 tm7 operation timing (cmn(bfcmn) = 000h) modification of table 10-5 real-time output port operating mode and output chapter 10 trigger real-time output port modification of figure 11-10 a/d conversion end interrupt request generation chapter 11 timing a/d converter addition of figure 12-2 block diagram of uart00 baud rate generator chapter 12 addition of figure 12-4 block diagram of uart01 baud rate generator serial interface (uart00, uart01) 13.2 configuration of serial interface chapter 13 modification of (1) serial i/o shift register 3 (sio3) serial interface (sio3) modification of table 17-1 status of each hardware after reset chapter 17 reset function modification of figure 18-4 flashpro ii/iii connection using 3-wire serial i/o chapter 18 modification of figure 18-5 flashpro ii/iii connection in uart mode pd78f0988 modification of figure 18-6 flashpro ii/iii connection using pseudo 3-wire serial i/o modification of figure a-1 development tool configuration appendix a a.1 language processing software development tools change in the status of device file df780988 from ?nder development?to ?evelopment completed a.3.1 hardware addition of the following products performance board ie-78k0-ns-pa (under development) emulation probe np-64gc-tq (development completed) conversion adapter tgc-064sap (development completed) change in the status of the following products from ?nder development?to ?evelopment completed pc card interface ie-70000-cd-if-a interface adapter ie-70000-pci-if addition of conversion adapter (tgc-064sap) package drawing 4th addition of the following products to the target products throughout pd780982(a), 780983(a), 780984(a), 780986(a), 780988(a) change of part number pd780982(a)gc- -ab8 pd780982gc(a)- -ab8 pd780983(a)gc- -ab8 pd780983gc(a)- -ab8 pd780984(a)gc- -ab8 pd780984gc(a)- -ab8 pd780986(a)gc- -ab8 pd780986gc(a)- -ab8 pd780988(a)gc- -ab8 pd780988gc(a)- -ab8 change of package name 64-pin plastic shrink dip (750 mil) 64-pin plastic sdip (19.05 mm (750)) modification of bit names and addition of caution to figure 10-6 format of real- chapter 10 real- time output port mode register 1 time output port addition of 11.6 how to read a/d converter characteristics tables chapter 11 a/d converter appendix d revision history user? manual u13029ej7v1ud 426 (3/6) edition contents applied to: 4th addition of figure 12-11 baud rate allowance error including sampling error chapter 12 serial (when k = 0) interface (uart00, addition of asis0n value description to table 12-5 receive error causes uart01) addition of remark to 14.2 interrupt sources and configuration chapter 14 addition of caution to figure 14-3 format of interrupt mask flag register interrupt functions addition of caution to figure 14-4 format of priority specification flag register addition of caution to figure 15-3 format of memory expansion wait setting chapter 15 register external device expansion function addition of caution to 18.3.1 selecting communication mode chapter 18 pd78f0988 a.3.1 hardware (1) when using the in-circuit emulator ie-78k0-ns: appendix a change in the status of ie-78k0-ns-pa from ?nder development?to ?evelopment development tools completed 5th deletion of one-shot pulse output from 16-bit timer/event counter function chapter 6 16-bit timer/event counter modification of figure 11-17 differential linearity error chapter 11 a/d converter 6th change of flash memory product from pd78f0988 to pd78f0988a, 78f0988a(a) throughout change of inttm01n timing in figure 6-18 timing of pulse width measurement chapter 6 16-bit operation with free-running counter and one capture register (with both timer/event edges specified) counter change of inttm01n timing in figure 6-20 cr01n capture operation with rising edge specified change of inttm00n and inttm01n timing in figure 6-21 timing of pulse width measurement operation with free-running counter (with both edges specified) change of inttm01n timing in figure 6-23 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) change of inttm01n timing in figure 6-25 timing of pulse width measurement operation by means of restart (with rising edge specified) change of cr01n interrupt value timing in figure 6-33 capture register data retention timing change of inttm00n timing in figure 6-34 operation timing of ovf0n flag addition of (11) to (14) to 11.5 notes on a/d converter chapter 11 a/d converter addition of caution to figure 14-2 format of interrupt request flag registers chapter 14 interrupt functions addition of 18.3 characteristics of flash memory chapter 18 addition of ?-wire serial i/o + hs?to table 18-4 communication modes pd78f0988a addition of ?riteback?to table 18-5 major functions of flash memory programming appendix d revision history 427 user? manual u13029ej7v1ud (4/6) edition contents applied to: 6th addition of figure 18-5 flashpro iii connection using 3-wire serial i/o chapter 18 (when handshake function is used) pd78f0988a addition of 18.5 pin connection modification of figure 18-14 self programming flowchart modification of table 18-7 entry ram area 18.6.5 entry ram area change of (d) erase time data addition of (f) writeback time modification of table 18-8 list of self-write subroutines modification of 18.6.6 self-write subroutines development tools appendix a addition of sp78k0 development tools change of part numbers of ra78k0, cc78k0, df780988, cc78k0-l, sm78k0, id78k0-ns, id78k0, rx78k0, and mx78k0 7th addition of package throughout pd780982gc- -8bs, 780983gc- -8bs, 780984gc- -8bs pd780986gc- -8bs, 780988gc- -8bs, 78f0988agc-8bs pd780982gc(a)- -8bs, 780983gc(a)- -8bs, 780984gc(a)- -8bs pd780986gc(a)- -8bs, 780988gc(a)- -8bs change of power supply voltage range as shown below. v dd = 4.0 to 5.5 v v dd = 3.0 to 5.5 v (expanded-specification products), v dd = 4.0 to 5.5 v (conventional products) change of system clock oscillation frequency (f x ) as shown below. f x = 8.38 mhz f x = 12 mhz (expanded-specification products only), f x =8.38 mhz change of minimum instruction execution time addition of 1.1 expanded-specification products and conventional products chapter 1 general 1.6 pin configuration (top view) addition of cautions 2 and 3 to 64-pin plastic sdip (19.05 mm (750)) addition of cautions 2 and 3 to 64-pin plastic qfp (14 x 14), 64-pin plastic lqfp (14 x 14) 3.1.2 internal data memory space chapter 3 addition of description on (1) internal high-speed ram and (2) internal expansion cpu architecture ram modification of table 5-2 relationship between cpu clock and minimum chapter 5 clock instruction execution time generator modification of figure 5-5 switching between system clock and cpu clock modification of figure 6-9 format of prescaler mode register 00 chapter 6 16-bit modification of figure 6-10 format of prescaler mode register 01 timer/event counter addition of figure 6-16 configuration diagram of ppg output addition of figure 6-17 ppg output operation timing modification of figure 7-7 format of timer clock select register 50 chapter 7 8-bit modification of figure 7-8 format of timer clock select register 51 timer/event counter modification of figure 7-9 format of timer clock select register 52 appendix d revision history user? manual u13029ej7v1ud 428 (5/6) edition contents applied to: 7th modification of figure 8-2 format of inverter timer control register 7 chapter 8 10-bit inverter control timer modification of table 9-1 loop detection time of watchdog timer chapter 9 modification of table 9-2 interval time watchdog timer modification of figure 9-2 format of watchdog timer clock select register modification of figure 9-4 format of oscillation stabilization time select register modification of table 9-4 loop detection time of watchdog timer modification of table 9-5 interval time of interval timer 11.2 configuration of a/d converter chapter 11 addition of register figure to (2) a/d conversion result register 0 (adcr0) a/d converter modification of figure 11-2 format of a/d converter mode register 0 11.5 notes on a/d converter addition of (6) input impedance of ani0 to ani7 pins modification of figure 12-9 format of baud rate generator control register 0 chapter 12 serial modification of figure 12-10 format of baud rate generator control register 1 interfaces uart00 12.4.2 asynchronous serial interface (uart) mode and uart01 modification of description modification of (1) register setting (c) baud rate generator control registers 0, 1 (brgc00, brgc01) modification of table 12-2 relationship between source clock of 5-bit counter and value of m (with uart00) modification of table 12-3 relationship between source clock of 5-bit counter and value of m (with uart01) modification of table 12-4 relationship between system clock and baud rate addition of remark to 12.4.3 infrared data transfer mode modification of table 12-7 baud rate that can be set in infrared data transfer mode modification of figure 13-2 format of serial operation mode register 3 chapter 13 serial interface sio3 addition of caution to 15.1 external device expansion function chapter 15 change of r/w to w in figure 15-2 format of memory expansion mode register external device expansion function modification of figure 16-1 format of oscillation stabilization time select register chapter 16 standby modification of figure 16-3 releasing halt mode by reset input function modification of figure 16-5 releasing stop mode by reset input revision of descriptions on flash memory programming as 18.3 flash memory chapter 18 features pd78f0988a 18.4.5 entry ram area modification of (c) write time data appendix d revision history 429 user? manual u13029ej7v1ud (6/6) edition contents applied to: 7th addition of chapter 20 electrical specifications chapter 20 electrical (expanded-specification products) specifications (expanded-specification products) addition of chapter 21 electrical specifications chapter 21 electrical (conventional products) specifications (conventional products) addition of chapter 22 package drawings chapter 22 package drawings addition of chapter 23 recommended soldering conditions chapter 23 recommended soldering conditions modification of appendix a development tools appendix a development tools addition of appendix b notes on designing target system appendix b notes on designing target system 7th edition modification of 1.4 ordering information chapter 1 general (modification addition of chapter 23 recommended soldering conditions chapter 23 version) recommended soldering conditions |
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